From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Tue, 6 Dec 2016 07:49:06 +0000 (-0800)
Subject: Added GP_DLATCH and GP_DLATCHI
X-Git-Tag: yosys-0.8~553^2^2~22
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8767cdcac95d30a454ba2bdd7c0d81083d3215ec;p=yosys.git

Added GP_DLATCH and GP_DLATCHI
---

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 1b3a66038..a59d17154 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -240,6 +240,24 @@ module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
 	end
 endmodule
 
+module GP_DLATCH(input D, input nCLK, output reg Q);
+	parameter [0:0] INIT = 1'bx;
+	initial Q = INIT;
+	always @(*) begin
+		if(!nCLK)
+			Q <= D;
+	end
+endmodule
+
+module GP_DLATCHI(input D, input nCLK, output reg Q);
+	parameter [0:0] INIT = 1'bx;
+	initial Q = INIT;
+	always @(*) begin
+		if(!nCLK)
+			Q <= ~D;
+	end
+endmodule
+
 module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
 	parameter [0:0] INIT = 1'bx;
 	initial Q = INIT;