From: Cole Poirier <colepoirier@gmail.com>
Date: Thu, 1 Oct 2020 23:17:57 +0000 (-0700)
Subject: icache.py add missing comb signal assignments per https://bugs.libre-soc.org/show_bug... 
X-Git-Tag: 24jan2021_ls180~258
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=876b59000e1b02567d0da35b48ec73938dd16251;p=soc.git

icache.py add missing comb signal assignments per https://bugs.libre-soc.org/show_bug.cgi?id=485#c32
---

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 46ba5d0c..75361d9b 100644
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -761,6 +761,12 @@ class ICache(Elaboratable):
             comb += req_is_hit.eq(is_hit)
             comb += req_is_miss.eq(~is_hit)
 
+        with m.Else():
+            comb += req_is_hit.eq(0)
+            comb += req_is_miss.eq(0)
+
+        comb += req_hit_way.eq(hit_way)
+
         # The way to replace on a miss
         with m.If(r.state == State.CLR_TAG):
             comb += replace_way.eq(plru_victim[r.store_index])