From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 2 Jun 2020 20:25:50 +0000 (+0100)
Subject: ok ok - for OP_BCREG put CTR in spr2 as well
X-Git-Tag: div_pipeline~637^2~35
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=87810631b7ecbd34ad89b2853bbdb763fe003633;p=soc.git

ok ok - for OP_BCREG put CTR in spr2 as well
---

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 84d5ed71..61caf556 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -64,12 +64,6 @@ class DecodeA(Elaboratable):
             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
                 comb += self.fast_out.ok.eq(1)
-        with m.Elif(op.internal_op == InternalOp.OP_BCREG):
-            xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
-            xo5 = self.dec.FormXL.XO[5] # 3.0B p38
-            with m.If(xo9 & ~xo5):
-                comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
-                comb += self.fast_out.ok.eq(1)
 
         # MFSPR or MTSPR: move-from / move-to SPRs
         with m.If((op.internal_op == InternalOp.OP_MFSPR) |
@@ -172,6 +166,9 @@ class DecodeB(Elaboratable):
             with m.Elif(xo5):
                 comb += self.fast_out.data.eq(FastRegs.TAR)
                 comb += self.fast_out.ok.eq(1)
+            with m.Else():
+                comb += self.fast_out.data.eq(FastRegs.CTR)
+                comb += self.fast_out.ok.eq(1)
 
         return m