From: Richard Kenner <kenner@gcc.gnu.org>
Date: Wed, 22 Apr 1992 22:48:22 +0000 (-0400)
Subject: entered into RCS
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=878e0c14c4eb4367b849edc896d914b00687aa59;p=gcc.git

entered into RCS

From-SVN: r818
---

diff --git a/gcc/config/a29k/a29k.c b/gcc/config/a29k/a29k.c
index fdf73dc0288..8f73f4f9529 100644
--- a/gcc/config/a29k/a29k.c
+++ b/gcc/config/a29k/a29k.c
@@ -183,24 +183,24 @@ float_const_operand (op, mode)
    general-purpose register.  */
 
 int
-gen_reg_or_float_constant_operand (op, mode)
+gpc_reg_or_float_constant_operand (op, mode)
      rtx op;
      enum machine_mode mode;
 {
-  return float_const_operand (op, mode) || gen_reg_operand (op, mode);
+  return float_const_operand (op, mode) || gpc_reg_operand (op, mode);
 }
 
 /* Returns 1 if OP is an integer constant of the proper mode or a
    general-purpose register.  */
 
 int
-gen_reg_or_integer_constant_operand (op, mode)
+gpc_reg_or_integer_constant_operand (op, mode)
      rtx op;
      enum machine_mode mode;
 {
   return ((GET_MODE (op) == VOIDmode
 	   && (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE))
-	  || gen_reg_operand (op, mode));
+	  || gpc_reg_operand (op, mode));
 }
      
 /* Returns 1 if OP is a special machine register.  */
@@ -228,7 +228,7 @@ accum_reg_operand (op, mode)
 /* Returns 1 if OP is a normal data register.  */
 
 int
-gen_reg_operand (op, mode)
+gpc_reg_operand (op, mode)
      rtx op;
      enum machine_mode mode;
 {
@@ -267,18 +267,18 @@ srcb_operand (op, mode)
   if (GET_MODE (op) != mode && mode != VOIDmode)
     return 0;
 
-  return gen_reg_operand (op, mode);
+  return gpc_reg_operand (op, mode);
 }
 
 /* Return 1 if OP is either an immediate or a general register.  This is used
    for the input operand of mtsr/mtrsim.  */
 
 int
-gen_reg_or_immediate_operand (op, mode)
+gpc_reg_or_immediate_operand (op, mode)
      rtx op;
      enum machine_mode;
 {
-  return gen_reg_operand (op, mode) || immediate_operand (op, mode);
+  return gpc_reg_operand (op, mode) || immediate_operand (op, mode);
 }
 
 /* Return 1 if OP can be used as the second operand of and AND insn.  This
@@ -370,7 +370,7 @@ out_operand (op, mode)
     op = SUBREG_REG (op);
 
   if (GET_CODE (op) == REG)
-    return (mode == SImode || gen_reg_operand (orig_op, mode)
+    return (mode == SImode || gpc_reg_operand (orig_op, mode)
 	    || (GET_MODE_CLASS (mode) == MODE_FLOAT
 		&& accum_reg_operand (orig_op, mode)));
 
diff --git a/gcc/config/a29k/a29k.md b/gcc/config/a29k/a29k.md
index c5707cd46ff..f4694f37c33 100644
--- a/gcc/config/a29k/a29k.md
+++ b/gcc/config/a29k/a29k.md
@@ -70,8 +70,8 @@
 
 ;; ADD
 (define_insn "addsi3"
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
-	(plus:SI (match_operand:SI 1 "gen_reg_operand" "%r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
 		 (match_operand:SI 2 "add_operand" "rI,N")))]
   ""
   "@
@@ -79,17 +79,17 @@
    sub %0,%1,%n2")
 
 (define_insn "adddi3"
-  [(set (match_operand:DI 0 "gen_reg_operand" "=r")
-	(plus:DI (match_operand:DI 1 "gen_reg_operand" "%r")
-		 (match_operand:DI 2 "gen_reg_operand" "r")))]
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
+		 (match_operand:DI 2 "gpc_reg_operand" "r")))]
   ""
   "add %L0,%L1,%L2\;addc %0,%1,%2"
   [(set_attr "type" "multi")])
 
 ;; AND/ANDN
 (define_insn "andsi3"
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
-	(and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
 		(match_operand:SI 2 "and_operand" "rI,K")))]
   ""
   "@
@@ -97,9 +97,9 @@
    andn %0,%1,%C2")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(and:SI (not:SI (match_operand:SI 1 "srcb_operand" "rI"))
-		(match_operand:SI 2 "gen_reg_operand" "r")))]
+		(match_operand:SI 2 "gpc_reg_operand" "r")))]
   ""
   "andn %0,%2,%1")
 
@@ -159,7 +159,7 @@
   [(set_attr "type" "call")])
 
 (define_expand "call_value"
-  [(parallel [(set (match_operand:SI 0 "gen_reg_operand" "")
+  [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
 		   (call (match_operand:SI 1 "" "")
 			 (match_operand 2 "" "")))
 		   (clobber (reg:SI 32))])
@@ -179,7 +179,7 @@
 }")
  
 (define_insn ""
-  [(set (match_operand 0 "gen_reg_operand" "=r")
+  [(set (match_operand 0 "gpc_reg_operand" "=r")
 	(call (match_operand:SI 1 "memory_operand" "m")
 	      (match_operand 2 "" "")))
    (clobber (reg:SI 32))]
@@ -198,7 +198,7 @@
   [(set_attr "type" "call")])
 
 (define_insn ""
-  [(set (match_operand 0 "gen_reg_operand" "=r")
+  [(set (match_operand 0 "gpc_reg_operand" "=r")
 	(call (mem:SI (match_operand:SI 1 "immediate_operand" "i"))
 	      (match_operand:SI 2 "general_operand" "g")))
    (clobber (reg:SI 32))]
@@ -227,14 +227,14 @@
 ;;
 ;; Many of these are generated from move insns.
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(and:SI (match_operand:SI 1 "immediate_operand" "i")
 		(const_int 65535)))]
   ""
   "const %0,%1")
 
 (define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
+  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
 			 (const_int 16)
 			 (match_operand:SI 1 "const_0_operand" ""))
 	(ashiftrt:SI (match_operand:SI 2 "immediate_operand" "i")
@@ -243,7 +243,7 @@
   "consth %0,%2")
 
 (define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
+  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
 			 (const_int 16)
 			 (match_operand:SI 1 "const_0_operand" ""))
 	(match_operand:SI 2 "cint_16_operand" "J"))]
@@ -254,16 +254,16 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(ior:SI (and:SI (match_operand:SI 1 "gen_reg_operand" "0")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ior:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "0")
 			(const_int 65535))
 		(match_operand:SI 2 "const_int_operand" "n")))]
   "(INTVAL (operands[1]) & 0xffff) == 0"
   "consth %0,%2")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(ior:SI (and:SI (match_operand:SI 1 "gen_reg_operand" "0")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ior:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "0")
 			(const_int 65535))
 		(and:SI (match_operand:SI 2 "immediate_operand" "i")
 			(const_int -65536))))]
@@ -273,25 +273,25 @@
 
 ;; CONVERT
 (define_insn "fix_truncsfsi2"
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(fix:SI (match_operand:SF 1 "register_operand" "r")))]
   ""
   "convert %0,%1,0,3,0,1")
 
 (define_insn "fix_truncdfsi2"
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(fix:SI (match_operand:DF 1 "register_operand" "r")))]
   ""
   "convert %0,%1,0,3,0,2")
 
 (define_insn "fixuns_truncsfsi2"
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(unsigned_fix:SI (match_operand:SF 1 "register_operand" "r")))]
   ""
   "convert %0,%1,1,3,0,1")
 
 (define_insn "fixuns_truncdfsi2"
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(unsigned_fix:SI (match_operand:DF 1 "register_operand" "r")))]
   ""
   "convert %0,%1,1,3,0,2")
@@ -310,39 +310,39 @@
 
 (define_insn "floatsisf2"
   [(set (match_operand:SF 0 "register_operand" "=r")
-	(float:SF (match_operand:SI 1 "gen_reg_operand" "r")))]
+	(float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
   ""
   "convert %0,%1,0,4,1,0")
 
 (define_insn "floatsidf2"
   [(set (match_operand:DF 0 "register_operand" "=r")
-	(float:DF (match_operand:SI 1 "gen_reg_operand" "r")))]
+	(float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
   ""
   "convert %0,%1,0,4,2,0")
 
 (define_insn "floatunssisf2"
   [(set (match_operand:SF 0 "register_operand" "=r")
-	(unsigned_float:SF (match_operand:SI 1 "gen_reg_operand" "r")))]
+	(unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
   ""
   "convert %0,%1,1,4,1,0")
 
 (define_insn "floatunssidf2"
   [(set (match_operand:DF 0 "register_operand" "=r")
-	(unsigned_float:DF (match_operand:SI 1 "gen_reg_operand" "r")))]
+	(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
   ""
   "convert %0,%1,1,4,2,0")
 
 ;; CPxxx, DEQ, DGT, DGE, FEQ, FGT, FGE
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(match_operator 3 "comparison_operator"
-			[(match_operand:SI 1 "gen_reg_operand" "r")
+			[(match_operand:SI 1 "gpc_reg_operand" "r")
 			 (match_operand:SI 2 "srcb_operand" "rI")]))]
   ""
   "cp%J3 %0,%1,%2")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(match_operator 3 "fp_comparison_operator"
 			[(match_operand:SF 1 "register_operand" "r")
 			 (match_operand:SF 2 "register_operand" "r")]))]
@@ -351,7 +351,7 @@
   [(set_attr "type" "fadd")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(match_operator 3 "fp_comparison_operator"
 			[(match_operand:DF 1 "register_operand" "r")
 			 (match_operand:DF 2 "register_operand" "r")]))]
@@ -403,12 +403,12 @@
 ;; 0 and remainder to operand 3.
 (define_expand "divmodsi4"
   [(set (match_dup 4)
-	(ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "")
+	(ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
 		     (const_int 31)))
-   (parallel [(set (match_operand:SI 0 "gen_reg_operand" "")
+   (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
 		   (div:SI (match_dup 1)
-			   (match_operand:SI 2 "gen_reg_operand" "")))
-	      (set (match_operand:SI 3 "gen_reg_operand" "")
+			   (match_operand:SI 2 "gpc_reg_operand" "")))
+	      (set (match_operand:SI 3 "gpc_reg_operand" "")
 		   (mod:SI (match_dup 1)
 			   (match_dup 2)))
 	      (use (match_dup 4))])]
@@ -419,9 +419,9 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(div:SI (match_operand:SI 1 "gen_reg_operand" "r")
-		(match_operand:SI 2 "gen_reg_operand" "r")))
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+		(match_operand:SI 2 "gpc_reg_operand" "r")))
    (set (match_operand:SI 3 "register_operand" "=q")
 	(mod:SI (match_dup 1)
 		(match_dup 2)))
@@ -433,10 +433,10 @@
 ;;
 ;; Similar to DIVIDE.
 (define_expand "udivmodsi4"
-  [(parallel [(set (match_operand:SI 0 "gen_reg_operand" "")
-		   (udiv:SI (match_operand:SI 1 "gen_reg_operand" "")
-			    (match_operand:SI 2 "gen_reg_operand" "")))
-	      (set (match_operand:SI 3 "gen_reg_operand" "")
+  [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
+		   (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
+			    (match_operand:SI 2 "gpc_reg_operand" "")))
+	      (set (match_operand:SI 3 "gpc_reg_operand" "")
 		   (umod:SI (match_dup 1)
 			    (match_dup 2)))
 	      (use (const_int 0))])]
@@ -444,9 +444,9 @@
   "")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(udiv:SI (match_operand:SI 1 "gen_reg_operand" "r")
-		 (match_operand:SI 2 "gen_reg_operand" "r")))
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+		 (match_operand:SI 2 "gpc_reg_operand" "r")))
    (set (match_operand:SI 3 "register_operand" "=q")
 	(umod:SI (match_dup 1)
 		 (match_dup 2)))
@@ -583,10 +583,10 @@
 
 ;; EXBYTE
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(ior:SI (and:SI (match_operand:SI 1 "srcb_operand" "rI")
 			(const_int -256))
-		(zero_extract:SI (match_operand:SI 2 "gen_reg_operand" "r")
+		(zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
 				 (const_int 8)
 				 (ashift:SI (match_operand:SI 3 "register_operand" "b")
 					    (const_int 3)))))]
@@ -594,8 +594,8 @@
   "exbyte %0,%2,%1")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			 (const_int 8)
 			 (ashift:SI (match_operand:SI 2 "register_operand" "b")
 				    (const_int 3))))]
@@ -603,10 +603,10 @@
   "exbyte %0,%1,0")
 
 (define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
+  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
 			 (const_int 8)
 			 (match_operand:SI 1 "const_24_operand" ""))
-	(zero_extract:SI (match_operand:SI 2 "gen_reg_operand" "r")
+	(zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
 			 (const_int 8)
 			 (ashift:SI (match_operand:SI 3 "register_operand" "b")
 				    (const_int 3))))]
@@ -614,8 +614,8 @@
   "exbyte %0,%2,%0")
 
 (define_expand "extzv"
-  [(set (match_operand:SI 0 "gen_reg_operand" "")
-	(zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
 			 (match_operand:SI 2 "general_operand" "")
 			 (match_operand:SI 3 "general_operand" "")))]
   ""
@@ -639,8 +639,8 @@
 }")
 
 (define_expand "extv"
-  [(set (match_operand:SI 0 "gen_reg_operand" "")
-	(zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
 			 (match_operand:SI 2 "general_operand" "")
 			 (match_operand:SI 3 "general_operand" "")))]
   ""
@@ -664,10 +664,10 @@
 
 ;; EXHW
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(ior:SI (and:SI (match_operand:SI 1 "srcb_operand" "rI")
 		(const_int -65536))
-		(zero_extract:SI (match_operand:SI 2 "gen_reg_operand" "r")
+		(zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
 				 (const_int 16)
 				 (ashift:SI (match_operand:SI 3 "register_operand" "b")
 					    (const_int 3)))))]
@@ -675,8 +675,8 @@
   "exhw %0,%2,%1")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			 (const_int 16)
 			 (ashift:SI (match_operand:SI 2 "register_operand" "b")
 				    (const_int 3))))]
@@ -684,10 +684,10 @@
   "exhw %0,%1,0")
 
 (define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
+  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
 			 (const_int 16)
 			 (match_operand:SI 1 "const_16_operand" ""))
-	(zero_extract:SI (match_operand:SI 2 "gen_reg_operand" "r")
+	(zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
 			 (const_int 16)
 			 (ashift:SI (match_operand:SI 3 "register_operand" "b")
 				    (const_int 3))))]
@@ -696,8 +696,8 @@
 
 ;; EXHWS
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(sign_extract:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(sign_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			 (const_int 16)
 			 (ashift:SI (match_operand:SI 2 "register_operand" "b")
 				    (const_int 3))))]
@@ -706,17 +706,17 @@
 
 ;; EXTRACT
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		   (reg:QI 178)))]
   ""
   "extract %0,%1,%1")
 
 (define_expand "rotlsi3"
   [(set (reg:QI 178)
-	(match_operand: SI 2 "gen_reg_or_immediate_operand" ""))
-   (set (match_operand:SI 0 "gen_reg_operand" "")
-	(rotate:SI (match_operand:SI 1 "gen_reg_operand" "")
+	(match_operand: SI 2 "gpc_reg_or_immediate_operand" ""))
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
+	(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
 		   (reg:QI 178)))]
   ""
   "
@@ -893,7 +893,7 @@
 
 ;; INBYTE
 (define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
+  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
 			 (const_int 8)
 			 (ashift:SI (match_operand:SI 2 "register_operand" "b")
 				    (const_int 3)))
@@ -902,11 +902,11 @@
   "inbyte %0,%0,%1")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(ior:SI (and:SI (not:SI (ashift:SI (const_int 255)
 					   (ashift:SI (match_operand:SI 3 "register_operand" "b")
 						      (const_int 3))))
-			(match_operand:SI 1 "gen_reg_operand" "r"))
+			(match_operand:SI 1 "gpc_reg_operand" "r"))
 		(ashift:SI (and:SI (match_operand:SI 2 "srcb_operand" "rI")
 				   (const_int 255))
 			   (match_operand:SI 4 "const_24_operand" ""))))]
@@ -914,11 +914,11 @@
   "inbyte %0,%1,%2")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(ior:SI (and:SI (not:SI (ashift:SI (const_int 255)
 					   (ashift:SI (match_operand:SI 3 "register_operand" "b")
 						      (const_int 3))))
-			(match_operand:SI 1 "gen_reg_operand" "r"))
+			(match_operand:SI 1 "gpc_reg_operand" "r"))
 		(ashift:SI (match_operand:SI 2 "srcb_operand" "rI")
 			   (match_operand:SI 4 "const_24_operand" ""))))]
   ""
@@ -926,7 +926,7 @@
 
 ;; INHW
 (define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
+  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
 			 (const_int 16)
 			 (ashift:SI (match_operand:SI 2 "register_operand" "b")
 				    (const_int 3)))
@@ -935,11 +935,11 @@
   "inhw %0,%0,%1")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(ior:SI (and:SI (not:SI (ashift:SI (const_int 65535)
 					   (ashift:SI (match_operand:SI 3 "register_operand" "b")
 						      (const_int 3))))
-			(match_operand:SI 1 "gen_reg_operand" "r"))
+			(match_operand:SI 1 "gpc_reg_operand" "r"))
 		(ashift:SI (and:SI (match_operand:SI 2 "srcb_operand" "rI")
 				   (const_int 65535))
 			   (match_operand:SI 4 "const_24_operand" ""))))]
@@ -947,18 +947,18 @@
   "inhw %0,%1,%2")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(ior:SI (and:SI (not:SI (ashift:SI (const_int 65535)
 					   (ashift:SI (match_operand:SI 3 "register_operand" "b")
 						      (const_int 3))))
-			(match_operand:SI 1 "gen_reg_operand" "r"))
+			(match_operand:SI 1 "gpc_reg_operand" "r"))
 		(ashift:SI (match_operand:SI 2 "srcb_operand" "rI")
 			   (match_operand:SI 4 "const_24_operand" ""))))]
   ""
   "inhw %0,%1,%2")
 
 (define_expand "insv"
-  [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "")
+  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "")
 			 (match_operand:SI 1 "general_operand" "")
 			 (match_operand:SI 2 "general_operand" ""))
 	(match_operand:SI 3 "srcb_operand" ""))]
@@ -984,8 +984,8 @@
 
 ;; LOAD (also used by move insn).
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(mem:SI (and:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(mem:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			(const_int -4))))
    (set (reg:SI 177)
 	(and:SI (match_dup 1)
@@ -995,8 +995,8 @@
   [(set_attr "type" "load")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(mem:SI (and:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(mem:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			(const_int -4))))
    (set (reg:SI 177)
 	(and:SI (match_dup 1)
@@ -1006,7 +1006,7 @@
   [(set_attr "type" "load")])
 
 (define_insn ""
-  [(set (match_operand 0 "gen_reg_operand" "=r")
+  [(set (match_operand 0 "gpc_reg_operand" "=r")
 	(match_operator 2 "extend_operator"
 			[(match_operand 1 "memory_operand" "m")]))]
   "TARGET_DW_ENABLE && GET_MODE (operands[0]) == GET_MODE (operands[2])"
@@ -1059,7 +1059,7 @@
 
 ;; Indicate that CR is used and is then clobbered.
 (define_insn ""
-  [(set (match_operand 0 "gen_reg_operand" "=r")
+  [(set (match_operand 0 "gpc_reg_operand" "=r")
 	(match_operand 1 "memory_operand" "m"))
    (use (reg:SI 179))
    (clobber (reg:SI 179))]
@@ -1070,7 +1070,7 @@
   [(set_attr "type" "load")])
 
 (define_insn ""
-  [(set (match_operand 0 "gen_reg_operand" "=&r")
+  [(set (match_operand 0 "gpc_reg_operand" "=&r")
 	(match_operand 1 "memory_operand" "m"))
    (use (reg:SI 179))
    (clobber (reg:SI 179))]
@@ -1082,7 +1082,7 @@
 
 (define_insn ""
   [(match_parallel 0 "load_multiple_operation"
-		   [(set (match_operand:SI 1 "gen_reg_operand" "=r")
+		   [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
 			 (match_operand:SI 2 "memory_operand" "m"))
 		    (use (reg:SI 179))
 		    (clobber (reg:SI 179))])]
@@ -1092,7 +1092,7 @@
 
 (define_insn ""
   [(match_parallel 0 "load_multiple_operation"
-		   [(set (match_operand:SI 1 "gen_reg_operand" "=&r")
+		   [(set (match_operand:SI 1 "gpc_reg_operand" "=&r")
 			 (match_operand:SI 2 "memory_operand" "m"))
 		    (use (reg:SI 179))
 		    (clobber (reg:SI 179))])]
@@ -1103,7 +1103,7 @@
 ;; MTSR (used also by move insn)
 (define_insn ""
   [(set (match_operand:SI 0 "spec_reg_operand" "=*h,*h")
-	(and:SI (match_operand:SI 1 "gen_reg_or_immediate_operand" "r,i")
+	(and:SI (match_operand:SI 1 "gpc_reg_or_immediate_operand" "r,i")
 		(match_operand:SI 2 "const_int_operand" "n,n")))]
   "masks_bits_for_special (operands[0], operands[2])"
   "@
@@ -1112,42 +1112,42 @@
 
 ;; MULTIPLY, MULTM, MULTMU
 (define_insn "mulsi3"
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(mult:SI (match_operand:SI 1 "gen_reg_operand" "%r")
-		 (match_operand:SI 2 "gen_reg_operand" "r")))]
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
+		 (match_operand:SI 2 "gpc_reg_operand" "r")))]
   ""
   "multiply %0,%1,%2")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(subreg:SI
 	 (mult:DI
-	  (sign_extend:DI (match_operand:SI 1 "gen_reg_operand" "%r"))
-	  (sign_extend:DI (match_operand:SI 2 "gen_reg_operand" "r"))) 0))]
+	  (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
+	  (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))) 0))]
   ""
   "multm %0,%1,%2")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(subreg:SI
 	 (mult:DI
-	  (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "%r"))
-	  (zero_extend:DI (match_operand:SI 2 "gen_reg_operand" "r"))) 0))]
+	  (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
+	  (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))) 0))]
   ""
   "multmu %0,%1,%2")
 
 (define_insn "mulsidi3"
-  [(set (match_operand:DI 0 "gen_reg_operand" "=r")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "gen_reg_operand" "r"))
-		 (sign_extend:DI (match_operand:SI 2 "gen_reg_operand" "r"))))]
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
+		 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
   ""
   "multiply %L0,%1,%2\;multm %0,%1,%2"
   [(set_attr "type" "multi")])
 
 (define_split
-  [(set (match_operand:DI 0 "gen_reg_operand" "")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "gen_reg_operand" ""))
-		 (sign_extend:DI (match_operand:SI 2 "gen_reg_operand" ""))))]
+  [(set (match_operand:DI 0 "gpc_reg_operand" "")
+	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
+		 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
   "reload_completed"
   [(set (match_dup 3)
 	(mult:SI (match_dup 1) (match_dup 2)))
@@ -1160,17 +1160,17 @@
   operands[4] = operand_subword (operands[1], 0, 1, DImode); } ")
 			    
 (define_insn "umulsidi3"
-  [(set (match_operand:DI 0 "gen_reg_operand" "=r")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "r"))
-		 (zero_extend:DI (match_operand:SI 2 "gen_reg_operand" "r"))))]
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
+		 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
   ""
   "multiplu %L0,%1,%2\;multmu %0,%1,%2"
   [(set_attr "type" "multi")])
 
 (define_split
-  [(set (match_operand:DI 0 "gen_reg_operand" "")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" ""))
-		 (zero_extend:DI (match_operand:SI 2 "gen_reg_operand" ""))))]
+  [(set (match_operand:DI 0 "gpc_reg_operand" "")
+	(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
+		 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
   "reload_completed"
   [(set (match_dup 3)
 	(mult:SI (match_dup 1) (match_dup 2)))
@@ -1183,58 +1183,58 @@
 			    
 ;; NAND
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "%r"))
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
 		(not:SI (match_operand:SI 2 "srcb_operand" "rI"))))]
   ""
   "nand %0,%1,%2")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
 		(match_operand:SI 2 "const_int_operand" "K")))]
   "((unsigned) ~ INTVAL (operands[2])) < 256"
   "nand %0,%1,%C2")
 
 ;; NOR
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "%r"))
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
 		(not:SI (match_operand:SI 2 "srcb_operand" "rI"))))]
   ""
   "nor %0,%1,%2")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
 		(match_operand:SI 2 "const_int_operand" "K")))]
   "((unsigned) ~ INTVAL (operands[2])) < 256"
   "nor %0,%1,%C2")
 
 (define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(not:SI (match_operand:SI 1 "gen_reg_operand" "r")))]
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
   ""
   "nor %0,%1,0")
 
 ;; OR/ORN
 (define_expand "iorsi3"
-  [(set (match_operand:SI 0 "gen_reg_operand" "")
-	(ior:SI (match_operand:SI 1 "gen_reg_operand" "")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
 		(match_operand:SI 2 "srcb_operand" "")))]
   ""
   "")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(ior:SI (match_operand:SI 1 "gen_reg_operand" "%r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
 		(match_operand:SI 2 "srcb_operand" "rI")))]
   "! TARGET_29050"
   "or %0,%1,%2")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
-	(ior:SI (match_operand:SI 1 "gen_reg_operand" "%r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
 		(match_operand:SI 2 "srcb_operand" "rI,K")))]
   "TARGET_29050"
   "@
@@ -1249,24 +1249,24 @@
   "aseq 0x40,gr1,gr1")
 
 (define_insn "ashlsi3"
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(ashift:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		   (match_operand:QI 2 "srcb_operand" "rn")))]
   ""
   "sll %0,%1,%Q2")
 
 ;; SRA
 (define_insn "ashrsi3"
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		     (match_operand:QI 2 "srcb_operand" "rn")))]
   ""
   "sra %0,%1,%Q2")
 
 ;; SRL
 (define_insn "lshrsi3"
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		     (match_operand:QI 2 "srcb_operand" "rn")))]
   ""
   "srl %0,%1,%Q2")
@@ -1276,17 +1276,17 @@
 ;; These somewhat bogus patterns exist to set OPT = 001/010 for partial-word
 ;; stores on systems with DW not set.
 (define_insn ""
-  [(set (mem:SI (and:SI (match_operand:SI 0 "gen_reg_operand" "r")
+  [(set (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "r")
 			(const_int -4)))
-	(match_operand:SI 1 "gen_reg_operand" "r"))]
+	(match_operand:SI 1 "gpc_reg_operand" "r"))]
   "! TARGET_DW_ENABLE"
   "store 0,1,%1,%0"
   [(set_attr "type" "store")])
 
 (define_insn ""
-  [(set (mem:SI (and:SI (match_operand:SI 0 "gen_reg_operand" "r")
+  [(set (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "r")
 			(const_int -3)))
-	(match_operand:SI 1 "gen_reg_operand" "r"))]
+	(match_operand:SI 1 "gpc_reg_operand" "r"))]
   "! TARGET_DW_ENABLE"
   "store 0,2,%1,%0"
   [(set_attr "type" "store")])
@@ -1396,7 +1396,7 @@
 
 (define_insn ""
   [(set (match_operand 0 "memory_operand" "=m")
-	(match_operand 1 "gen_reg_operand" "r"))
+	(match_operand 1 "gpc_reg_operand" "r"))
    (clobber (reg:SI 179))]
   "!TARGET_NO_STOREM_BUG
    && GET_MODE (operands[0]) == GET_MODE (operands[1])
@@ -1407,7 +1407,7 @@
 (define_insn ""
   [(match_parallel 0 "store_multiple_operation"
 		   [(set (match_operand:SI 1 "memory_operand" "=m")
-			 (match_operand:SI 2 "gen_reg_operand" "r"))
+			 (match_operand:SI 2 "gpc_reg_operand" "r"))
 		    (clobber (reg:SI 179))])]
   "!TARGET_NO_STOREM_BUG"
   "mtsrim cr,%V0\;storem 0,0,%2,%1"
@@ -1415,7 +1415,7 @@
 
 (define_insn ""
   [(set (match_operand 0 "memory_operand" "=m")
-	(match_operand 1 "gen_reg_operand" "r"))
+	(match_operand 1 "gpc_reg_operand" "r"))
    (use (reg:SI 179))
    (clobber (reg:SI 179))]
   "TARGET_NO_STOREM_BUG
@@ -1427,7 +1427,7 @@
 (define_insn ""
   [(match_parallel 0 "store_multiple_operation"
 		   [(set (match_operand:SI 1 "memory_operand" "=m")
-			 (match_operand:SI 2 "gen_reg_operand" "r"))
+			 (match_operand:SI 2 "gpc_reg_operand" "r"))
 		    (use (reg:SI 179))
 		    (clobber (reg:SI 179))])]
   "TARGET_NO_STOREM_BUG"
@@ -1439,7 +1439,7 @@
 ;; Either operand can be a register or an 8-bit constant, but both cannot be
 ;; constants (can't usually occur anyway).
 (define_expand "subsi3"
-  [(set (match_operand:SI 0 "gen_reg_operand" "")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
 	(minus:SI (match_operand:SI 1 "srcb_operand" "")
 		  (match_operand:SI 2 "srcb_operand" "")))]
   ""
@@ -1451,7 +1451,7 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(minus:SI (match_operand:SI 1 "srcb_operand" "r,I")
 		  (match_operand:SI 2 "srcb_operand" "rI,r")))]
   "register_operand (operands[1], SImode)
@@ -1461,39 +1461,39 @@
    subr %0,%2,%1")
 
 (define_insn "subdi3"
-  [(set (match_operand:DI 0 "gen_reg_operand" "=r")
-	(minus:DI (match_operand:DI 1 "gen_reg_operand" "r")
-		  (match_operand:DI 2 "gen_reg_operand" "r")))]
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+		  (match_operand:DI 2 "gpc_reg_operand" "r")))]
   ""
   "sub %L0,%L1,%L2\;subc %0,%1,%2"
   [(set_attr "type" "multi")])
 
 ;; SUBR (also used above in SUB)
 (define_insn "negdi2"
-  [(set (match_operand:DI 0 "gen_reg_operand" "=r")
-	(neg:DI (match_operand:DI 1 "gen_reg_operand" "r")))]
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
   ""
   "subr %L0,%L1,0\;subrc %0,%1,0"
   [(set_attr "type" "multi")])
 
 (define_insn "negsi2"
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(neg:SI (match_operand:SI 1 "gen_reg_operand" "r")))]
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
   ""
   "subr %0,%1,0")
 
 ;; XNOR
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
 			(match_operand:SI 2 "srcb_operand" "rI"))))]
   ""
   "xnor %0,%1,%2")
 
 ;; XOR
 (define_insn "xorsi3"
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(xor:SI (match_operand:SI 1 "gen_reg_operand" "%r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
 		(match_operand:SI 2 "srcb_operand" "rI")))]
   ""
   "xor %0,%1,%2")
@@ -1567,28 +1567,28 @@
 
 ;; Sign extend and truncation operations.
 (define_insn "zero_extendqihi2"
-  [(set (match_operand:HI 0 "gen_reg_operand" "=r")
-	(zero_extend:HI (match_operand:QI 1 "gen_reg_operand" "r")))]
+  [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
+	(zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
   ""
   "and %0,%1,255")
 
 (define_insn "zero_extendqisi2"
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "r")))]
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
   ""
   "and %0,%1,255")
 
 (define_insn "zero_extendhisi2"
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "0")))]
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "0")))]
   ""
   "consth %0,0")
 
 (define_expand "extendqihi2"
   [(set (match_dup 2)
-	(ashift:SI (match_operand:QI 1 "gen_reg_operand" "")
+	(ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
 		   (const_int 24)))
-   (set (match_operand:HI 0 "gen_reg_operand" "")
+   (set (match_operand:HI 0 "gpc_reg_operand" "")
 	(ashiftrt:SI (match_dup 2)
 		     (const_int 24)))]
   ""
@@ -1599,9 +1599,9 @@
 
 (define_expand "extendqisi2"
   [(set (match_dup 2)
-	(ashift:SI (match_operand:QI 1 "gen_reg_operand" "")
+	(ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
 		   (const_int 24)))
-   (set (match_operand:SI 0 "gen_reg_operand" "")
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(ashiftrt:SI (match_dup 2)
 		     (const_int 24)))]
   ""
@@ -1611,9 +1611,9 @@
 
 (define_expand "extendhisi2"
   [(set (match_dup 2)
-	(ashift:SI (match_operand:HI 1 "gen_reg_operand" "")
+	(ashift:SI (match_operand:HI 1 "gpc_reg_operand" "")
 		   (const_int 16)))
-   (set (match_operand:SI 0 "gen_reg_operand" "")
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(ashiftrt:SI (match_dup 2)
 		     (const_int 16)))]
   ""
@@ -1632,7 +1632,7 @@
   ""
   "
 {
-  if (GET_CODE (operands[0]) == MEM && ! gen_reg_operand (operands[1], SImode))
+  if (GET_CODE (operands[0]) == MEM && ! gpc_reg_operand (operands[1], SImode))
     operands[1] = copy_to_mode_reg (SImode, operands[1]);
   else if (spec_reg_operand (operands[0], SImode)
 	   && ! (register_operand (operands[1], SImode)
@@ -1641,7 +1641,7 @@
 }")
 
 (define_split
-  [(set (match_operand:SI 0 "gen_reg_operand" "")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
 	(match_operand:SI 1 "long_const_operand" ""))]
   ""
   [(set (match_dup 0)
@@ -1659,12 +1659,12 @@
 ;; where they aren't.
 (define_expand "loadhi"
   [(parallel [(set (match_dup 2)
-		   (mem:SI (and:SI (match_operand:SI 0 "gen_reg_operand" "")
+		   (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "")
 				   (const_int -4))))
 	      (set (reg:SI 177)
 		   (and:SI (match_dup 0)
 			   (const_int 2)))])
-   (set (match_operand:HI 1 "gen_reg_operand" "")
+   (set (match_operand:HI 1 "gpc_reg_operand" "")
 	(zero_extract:SI (match_dup 2)
 			 (const_int 16)
 			 (ashift:SI (reg:SI 177)
@@ -1681,7 +1681,7 @@
 
 (define_expand "storehinhww"
   [(parallel [(set (match_dup 2)
-		   (mem:SI (and:SI (match_operand:SI 0 "gen_reg_operand" "")
+		   (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "")
 				   (const_int -4))))
 	      (set (reg:SI 177)
 		   (and:SI (match_dup 0)
@@ -1690,7 +1690,7 @@
 			 (const_int 8)
 			 (ashift:SI (reg:SI 177)
 				    (const_int 3)))
-	(match_operand:HI 1 "gen_reg_operand" ""))
+	(match_operand:HI 1 "gpc_reg_operand" ""))
    (set (mem:SI (match_dup 0))
 	(match_dup 2))]
   ""
@@ -1705,13 +1705,13 @@
 
 (define_expand "storehihww"
   [(set (reg:SI 177)
-	(and:SI (match_operand:SI 0 "gen_reg_operand" "")
+	(and:SI (match_operand:SI 0 "gpc_reg_operand" "")
 		(const_int 3)))
    (set (match_dup 2)
 	(ior:SI (and:SI (not:SI (ashift:SI (const_int 65535)
 					   (ashift:SI (reg:SI 177)
 						      (const_int 3))))
-			(match_operand:HI 1 "gen_reg_operand" ""))
+			(match_operand:HI 1 "gpc_reg_operand" ""))
 		(ashift:SI (and:SI (match_dup 1)
 				   (const_int 65535))
 			   (ashift:SI (reg:SI 177)
@@ -1736,7 +1736,7 @@
   "
 { if (GET_CODE (operands[0]) == MEM) 
     {
-      if (! gen_reg_operand (operands[1], HImode))
+      if (! gpc_reg_operand (operands[1], HImode))
 	operands[1] = copy_to_mode_reg (HImode, operands[1]);
       if (! TARGET_DW_ENABLE)
 	{
@@ -1760,12 +1760,12 @@
 ;; Subroutines to load/store bytes.  Use TAV (gr121) as scratch.
 (define_expand "loadqi"
   [(parallel [(set (match_dup 2)
-		   (mem:SI (and:SI (match_operand:SI 0 "gen_reg_operand" "")
+		   (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "")
 				   (const_int -4))))
 	      (set (reg:SI 177)
 		   (and:SI (match_dup 0)
 			   (const_int 3)))])
-   (set (match_operand:QI 1 "gen_reg_operand" "")
+   (set (match_operand:QI 1 "gpc_reg_operand" "")
 	(zero_extract:SI (match_dup 2)
 			 (const_int 8)
 			 (ashift:SI (reg:SI 177)
@@ -1782,7 +1782,7 @@
 
 (define_expand "storeqinhww"
   [(parallel [(set (match_dup 2)
-		   (mem:SI (and:SI (match_operand:SI 0 "gen_reg_operand" "")
+		   (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "")
 				   (const_int -4))))
 	      (set (reg:SI 177)
 		   (and:SI (match_dup 0)
@@ -1791,7 +1791,7 @@
 			 (const_int 8)
 			 (ashift:SI (reg:SI 177)
 				    (const_int 3)))
-	(match_operand:QI 1 "gen_reg_operand" ""))
+	(match_operand:QI 1 "gpc_reg_operand" ""))
    (set (mem:SI (match_dup 0))
 	(match_dup 2))]
   ""
@@ -1806,13 +1806,13 @@
 
 (define_expand "storeqihww"
   [(set (reg:SI 177)
-	(and:SI (match_operand:SI 0 "gen_reg_operand" "")
+	(and:SI (match_operand:SI 0 "gpc_reg_operand" "")
 		(const_int 3)))
    (set (match_dup 2)
 	(ior:SI (and:SI (not:SI (ashift:SI (const_int 255)
 					   (ashift:SI (reg:SI 177)
 						      (const_int 3))))
-			(match_operand:HI 1 "gen_reg_operand" ""))
+			(match_operand:HI 1 "gpc_reg_operand" ""))
 		(ashift:SI (and:SI (match_dup 1)
 				   (const_int 255))
 			   (ashift:SI (reg:SI 177)
@@ -1837,7 +1837,7 @@
   "
 { if (GET_CODE (operands[0]) == MEM)
     {
-      if (! gen_reg_operand (operands[1], QImode))
+      if (! gpc_reg_operand (operands[1], QImode))
 	operands[1] = copy_to_mode_reg (QImode, operands[1]);
       if (! TARGET_DW_ENABLE)
 	{
@@ -1865,8 +1865,8 @@
 (define_insn ""
   [(set (match_operand:SF 0 "out_operand" "=r,r,r,r,m")
 	(match_operand:SF 1 "in_operand" "r,E,F,m,r"))]
-  "(gen_reg_operand (operands[0], SFmode)
-    || gen_reg_operand (operands[1], SFmode))
+  "(gpc_reg_operand (operands[0], SFmode)
+    || gpc_reg_operand (operands[1], SFmode))
    && ! TARGET_29050"
   "@
    sll %0,%1,0
@@ -1879,8 +1879,8 @@
 (define_insn ""
   [(set (match_operand:SF 0 "out_operand" "=r,r,r,r,m,*a,r")
 	(match_operand:SF 1 "in_operand" "r,E,F,m,r,r,*a"))]
-  "(gen_reg_operand (operands[0], SFmode)
-    || gen_reg_operand (operands[1], SFmode))
+  "(gpc_reg_operand (operands[0], SFmode)
+    || gpc_reg_operand (operands[1], SFmode))
    && TARGET_29050"
   "@
    sll %0,%1,0
@@ -1911,8 +1911,8 @@
   [(set (match_operand:DF 0 "out_operand" "=r,r,r,m")
 	(match_operand:DF 1 "in_operand" "rE,F,m,r"))
    (clobber (reg:SI 179))]
-  "(gen_reg_operand (operands[0], DFmode)
-    || gen_reg_operand (operands[1], DFmode))
+  "(gpc_reg_operand (operands[0], DFmode)
+    || gpc_reg_operand (operands[1], DFmode))
    && ! TARGET_29050"
   "@
    #
@@ -1925,8 +1925,8 @@
   [(set (match_operand:DF 0 "out_operand" "=r,r,&r,m,*a,r")
 	(match_operand:DF 1 "in_operand" "rE,F,m,r,r,*a"))
    (clobber (reg:SI 179))]
-  "(gen_reg_operand (operands[0], DFmode)
-    || gen_reg_operand (operands[1], DFmode))
+  "(gpc_reg_operand (operands[0], DFmode)
+    || gpc_reg_operand (operands[1], DFmode))
    && TARGET_29050"
   "@
    #
@@ -1945,8 +1945,8 @@
 ;; the lowest register of the first operand is the highest register of the
 ;; second operand.
 (define_split
-  [(set (match_operand:DF 0 "gen_reg_operand" "")
-	(match_operand:DF 1 "gen_reg_or_float_constant_operand" ""))
+  [(set (match_operand:DF 0 "gpc_reg_operand" "")
+	(match_operand:DF 1 "gpc_reg_or_float_constant_operand" ""))
    (clobber (reg:SI 179))]
   "reload_completed"
   [(set (match_dup 2) (match_dup 3))
@@ -1992,8 +1992,8 @@
   [(set (match_operand:DI 0 "out_operand" "=r,r,m")
 	(match_operand:DI 1 "in_operand" "rn,m,r"))
    (clobber (reg:SI 179))]
-  "(gen_reg_operand (operands[0], DImode)
-     || gen_reg_operand (operands[1], DImode))
+  "(gpc_reg_operand (operands[0], DImode)
+     || gpc_reg_operand (operands[1], DImode))
    && ! TARGET_29050"
   "@
    #
@@ -2005,8 +2005,8 @@
   [(set (match_operand:DI 0 "out_operand" "=r,&r,m")
 	(match_operand:DI 1 "in_operand" "rn,m,r"))
    (clobber (reg:SI 179))]
-  "(gen_reg_operand (operands[0], DImode)
-     || gen_reg_operand (operands[1], DImode))
+  "(gpc_reg_operand (operands[0], DImode)
+     || gpc_reg_operand (operands[1], DImode))
    && TARGET_29050"
   "@
    #
@@ -2015,8 +2015,8 @@
   [(set_attr "type" "multi")])
 
 (define_split
-  [(set (match_operand:DI 0 "gen_reg_operand" "")
-	(match_operand:DI 1 "gen_reg_or_integer_constant_operand" ""))
+  [(set (match_operand:DI 0 "gpc_reg_operand" "")
+	(match_operand:DI 1 "gpc_reg_or_integer_constant_operand" ""))
    (clobber (reg:SI 179))]
   "reload_completed"
   [(set (match_dup 2) (match_dup 3))
@@ -2058,8 +2058,8 @@
   [(set (match_operand:TI 0 "out_operand" "=r,r,m")
 	(match_operand:TI 1 "in_operand" "r,m,r"))
    (clobber (reg:SI 179))]
-  "(gen_reg_operand (operands[0], TImode)
-    || gen_reg_operand (operands[1], TImode))
+  "(gpc_reg_operand (operands[0], TImode)
+    || gpc_reg_operand (operands[1], TImode))
    && ! TARGET_29050"
   "@
    #
@@ -2071,8 +2071,8 @@
   [(set (match_operand:TI 0 "out_operand" "=r,&r,m")
 	(match_operand:TI 1 "in_operand" "r,m,r"))
    (clobber (reg:SI 179))]
-  "(gen_reg_operand (operands[0], TImode)
-    || gen_reg_operand (operands[1], TImode))
+  "(gpc_reg_operand (operands[0], TImode)
+    || gpc_reg_operand (operands[1], TImode))
    && TARGET_29050"
   "@
    #
@@ -2081,8 +2081,8 @@
   [(set_attr "type" "multi,multi,multi")])
 
 (define_split
-  [(set (match_operand:TI 0 "gen_reg_operand" "")
-	(match_operand:TI 1 "gen_reg_operand" ""))
+  [(set (match_operand:TI 0 "gpc_reg_operand" "")
+	(match_operand:TI 1 "gpc_reg_operand" ""))
    (clobber (reg:SI 179))]
   "reload_completed"
   [(set (match_dup 2) (match_dup 3))
@@ -2132,8 +2132,8 @@
 (define_insn ""
   [(set (match_operand:SI 0 "out_operand" "=r,r,r,r,r,r,r,m,*h,*h")
         (match_operand:SI 1 "in_operand" "r,J,M,O,i,m,*h,r,r,J"))]
-  "(gen_reg_operand (operands[0], SImode)
-    || gen_reg_operand (operands[1], SImode)
+  "(gpc_reg_operand (operands[0], SImode)
+    || gpc_reg_operand (operands[1], SImode)
     || (spec_reg_operand (operands[0], SImode)
         && cint_16_operand (operands[1], SImode)))
    && ! TARGET_29050"
@@ -2153,8 +2153,8 @@
 (define_insn ""
   [(set (match_operand:SI 0 "out_operand" "=r,r,r,r,r,r,r,m,*h,*h")
         (match_operand:SI 1 "in_operand" "r,J,M,O,i,m,*h,r,r,J"))]
-  "(gen_reg_operand (operands[0], SImode)
-    || gen_reg_operand (operands[1], SImode)
+  "(gpc_reg_operand (operands[0], SImode)
+    || gpc_reg_operand (operands[1], SImode)
     || (spec_reg_operand (operands[0], SImode)
         && cint_16_operand (operands[1], SImode)))
    && TARGET_29050"
@@ -2174,8 +2174,8 @@
 (define_insn ""
   [(set (match_operand:HI 0 "out_operand" "=r,r,r,m,r,*h,*h")
         (match_operand:HI 1 "in_operand" "r,i,m,r,*h,r,i"))]
-  "gen_reg_operand (operands[0], HImode)
-   || gen_reg_operand (operands[1], HImode)"
+  "gpc_reg_operand (operands[0], HImode)
+   || gpc_reg_operand (operands[1], HImode)"
   "@
    sll %0,%1,0
    const %0,%1
@@ -2189,8 +2189,8 @@
 (define_insn ""
   [(set (match_operand:QI 0 "out_operand" "=r,r,r,m,r,*h,*h")
         (match_operand:QI 1 "in_operand" "r,i,m,r,*h,r,i"))]
-  "gen_reg_operand (operands[0], QImode)
-   || gen_reg_operand (operands[1], QImode)"
+  "gpc_reg_operand (operands[0], QImode)
+   || gpc_reg_operand (operands[1], QImode)"
   "@
    sll %0,%1,0
    const %0,%1
@@ -2257,7 +2257,7 @@
 ;; is needed.
 (define_expand "cmpsi"
   [(set (cc0)
-	(compare (match_operand:SI 0 "gen_reg_operand" "")
+	(compare (match_operand:SI 0 "gpc_reg_operand" "")
 		 (match_operand:SI 1 "srcb_operand" "")))]
   ""
   "
@@ -2270,8 +2270,8 @@
 
 (define_expand "cmpsf"
   [(set (cc0)
-	(compare (match_operand:SF 0 "gen_reg_operand" "")
-		 (match_operand:SF 1 "gen_reg_operand" "")))]
+	(compare (match_operand:SF 0 "gpc_reg_operand" "")
+		 (match_operand:SF 1 "gpc_reg_operand" "")))]
   ""
   "
 {
@@ -2283,8 +2283,8 @@
 
 (define_expand "cmpdf"
   [(set (cc0)
-	(compare (match_operand:DF 0 "gen_reg_operand" "")
-		 (match_operand:DF 1 "gen_reg_operand" "")))]
+	(compare (match_operand:DF 0 "gpc_reg_operand" "")
+		 (match_operand:DF 1 "gpc_reg_operand" "")))]
   ""
   "
 {
@@ -2487,7 +2487,7 @@
 }")
 
 (define_expand "seq"
-  [(set (match_operand:SI 0 "gen_reg_operand" "")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
 	(eq:SI (match_dup 1) (match_dup 2)))]
   ""
   "
@@ -2501,9 +2501,9 @@
 ;; compare and then write an insn to reverse the test.
 (define_expand "sne_fp"
   [(set (match_dup 3)
-	(eq:SI (match_operand 1 "gen_reg_operand" "")
-	       (match_operand 2 "gen_reg_operand" "")))
-   (set (match_operand:SI 0 "gen_reg_operand" "")
+	(eq:SI (match_operand 1 "gpc_reg_operand" "")
+	       (match_operand 2 "gpc_reg_operand" "")))
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(ge:SI (match_dup 3) (const_int 0)))]
   ""
   "
@@ -2511,7 +2511,7 @@
 }");
 
 (define_expand "sne"
-  [(set (match_operand:SI 0 "gen_reg_operand" "")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
 	(ne:SI (match_dup 1) (match_dup 2)))]
   ""
   "
@@ -2529,7 +2529,7 @@
 ;; We don't have a floating-point "lt" insn, so use "gt" and swap the
 ;; operands, the same as we do "blt".
 (define_expand "slt"
-  [(set (match_operand:SI 0 "gen_reg_operand" "")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
 	(match_dup 1))]
   ""
   "
@@ -2542,7 +2542,7 @@
 
 ;; Similarly for "le"
 (define_expand "sle"
-  [(set (match_operand:SI 0 "gen_reg_operand" "")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
 	(match_dup 1))]
   ""
   "
@@ -2554,7 +2554,7 @@
 }")
 
 (define_expand "sltu"
-  [(set (match_operand:SI 0 "gen_reg_operand" "")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
 	(ltu:SI (match_dup 1) (match_dup 2)))]
   ""
   "
@@ -2564,7 +2564,7 @@
 }")
 
 (define_expand "sleu"
-  [(set (match_operand:SI 0 "gen_reg_operand" "")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
 	(leu:SI (match_dup 1) (match_dup 2)))]
   ""
   "
@@ -2574,7 +2574,7 @@
 }")
 
 (define_expand "sgt"
-  [(set (match_operand:SI 0 "gen_reg_operand" "")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
 	(gt:SI (match_dup 1) (match_dup 2)))]
   ""
   "
@@ -2584,7 +2584,7 @@
 }")
 
 (define_expand "sge"
-  [(set (match_operand:SI 0 "gen_reg_operand" "")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
 	(ge:SI (match_dup 1) (match_dup 2)))]
   ""
   "
@@ -2594,7 +2594,7 @@
 }")
 		 
 (define_expand "sgtu"
-  [(set (match_operand:SI 0 "gen_reg_operand" "")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
 	(gtu:SI (match_dup 1) (match_dup 2)))]
   ""
   "
@@ -2604,7 +2604,7 @@
 }")
 
 (define_expand "sgeu"
-  [(set (match_operand:SI 0 "gen_reg_operand" "")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
 	(geu:SI (match_dup 1) (match_dup 2)))]
   ""
   "
@@ -2617,7 +2617,7 @@
 (define_insn ""
   [(set (pc)
 	(if_then_else (match_operator 0 "branch_operator"
-				      [(match_operand:SI 1 "gen_reg_operand" "r")
+				      [(match_operand:SI 1 "gpc_reg_operand" "r")
 				       (const_int 0)])
 		      (label_ref (match_operand 2 "" ""))
 		      (pc)))]
@@ -2628,7 +2628,7 @@
 (define_insn ""
   [(set (pc)
 	(if_then_else (match_operator 0 "branch_operator"
-				      [(match_operand:SI 1 "gen_reg_operand" "r")
+				      [(match_operand:SI 1 "gpc_reg_operand" "r")
 				       (const_int 0)])
 		      (return)
 		      (pc)))]
@@ -2639,7 +2639,7 @@
 (define_insn ""
   [(set (pc)
 	(if_then_else (match_operator 0 "branch_operator"
-				      [(match_operand:SI 1 "gen_reg_operand" "r")
+				      [(match_operand:SI 1 "gpc_reg_operand" "r")
 				       (const_int 0)])
 		      (pc)
 		      (label_ref (match_operand 2 "" ""))))]
@@ -2650,7 +2650,7 @@
 (define_insn ""
   [(set (pc)
 	(if_then_else (match_operator 0 "branch_operator"
-				      [(match_operand:SI 1 "gen_reg_operand" "r")
+				      [(match_operand:SI 1 "gpc_reg_operand" "r")
 				       (const_int 0)])
 		      (pc)
 		      (return)))]
@@ -2673,14 +2673,14 @@
 
 (define_insn "indirect_jump"
   [(set (pc)
-	(match_operand:SI 0 "gen_reg_operand" "r"))]
+	(match_operand:SI 0 "gpc_reg_operand" "r"))]
   ""
   "jmpi %0%#"
   [(set_attr "type" "branch")])
 
 (define_insn "tablejump"
   [(set (pc)
-	(match_operand:SI 0 "gen_reg_operand" "r"))
+	(match_operand:SI 0 "gpc_reg_operand" "r"))
    (use (label_ref (match_operand 1 "" "")))]
   ""
   "jmpi %0%#"
@@ -2689,7 +2689,7 @@
 ;; JMPFDEC
 (define_insn ""
   [(set (pc)
-	(if_then_else (ge (match_operand:SI 0 "gen_reg_operand" "r")
+	(if_then_else (ge (match_operand:SI 0 "gpc_reg_operand" "r")
 			  (const_int 0))
 		      (label_ref (match_operand 1 "" ""))
 		      (pc)))