From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 2 Oct 2018 15:01:22 +0000 (+0100)
Subject: start work on parallelsing LOAD, pass in parameter to reinterpret immed
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=878f4926bfabfdb77361d691693f3824ac7b5343;p=riscv-isa-sim.git

start work on parallelsing LOAD, pass in parameter to reinterpret immed
---

diff --git a/id_regs.py b/id_regs.py
index 435b871..21a3faa 100644
--- a/id_regs.py
+++ b/id_regs.py
@@ -111,8 +111,8 @@ if __name__ == '__main__':
             # help identify type of register
             if insn in ['beq', 'bne', 'blt', 'bltu', 'bge', 'bgeu']:
                 txt += "#define INSN_TYPE_BRANCH\n"
-            elif insn in ['c_ld', 'c_bnez']:
-                txt += "\n#define INSN_TYPE_C_BRANCH\n"
+            if insn in ['lb', 'lbu', 'lw', 'lwu', 'ld', 'ldu']:
+                txt += "#define INSN_TYPE_LOAD\n"
             elif insn in ['c_lwsp', 'c_ldsp', 'c_lqsp', 'c_flwsp', 'c_fldsp']:
                 txt += "\n#define INSN_TYPE_C_STACK_LD\n"
             elif insn in ['c_swsp', 'c_sdsp', 'c_sqsp', 'c_fswsp', 'c_fsdsp']:
diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index 7e98462..4a547a6 100644
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -19,8 +19,13 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
   // REGS_PATTERN is generated by id_regs.py (per opcode)
   unsigned int floatintmap = REGS_PATTERN;
   reg_t dest_pred = ~0x0;
+  bool ldimm_sv = false;
+#ifdef INSN_TYPE_LOAD
+  bool ldimm_sv = true;
+#endif
   sv_insn_t insn(p, bits, floatintmap,
-                 dest_pred, dest_pred, dest_pred, dest_pred);
+                 dest_pred, dest_pred, dest_pred, dest_pred,
+                 ldimm_sv);
   bool zeroing;
 #if defined(USING_REG_RD) || defined(USING_REG_FRD)
   // use the ORIGINAL, i.e. NON-REDIRECTED, register here
@@ -63,7 +68,8 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
 #if defined(USING_REG_FRD)
         fprintf(stderr, "reg %s %x vloop %d vlen %d stop %d pred %lx rd%lx\n",
                 xstr(INSN), INSNCODE, voffs, vlen, insn.stop_vloop(),
-                dest_pred & (1<<voffs), READ_FREG(insn._rd()));
+                dest_pred & (1<<voffs),
+                (READ_FREG(insn._rd())));
 #endif
       }
       insn.reset_caches(); // ready to increment offsets in next iteration
diff --git a/riscv/sv.cc b/riscv/sv.cc
index 90ef354..bb791b8 100644
--- a/riscv/sv.cc
+++ b/riscv/sv.cc
@@ -165,3 +165,11 @@ uint64_t sv_insn_t::predicated(uint64_t reg, int offs, uint64_t pred)
     return 0;
 }
 
+uint64_t sv_insn_t::i_imm()
+{
+    if (ldst_imm_mode == false)
+    {
+        return insn_t::i_imm();
+    }
+    return insn_t::i_imm(); // TODO
+}
diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index 5d2b2fc..cf23ffd 100644
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -21,7 +21,8 @@ class sv_insn_t: public insn_t
 {
 public:
   sv_insn_t(processor_t *pr, insn_bits_t bits, unsigned int f,
-            uint64_t &p_rd, uint64_t &p_rs1, uint64_t &p_rs2, uint64_t &p_rs3) :
+            uint64_t &p_rd, uint64_t &p_rs1, uint64_t &p_rs2, uint64_t &p_rs3,
+            bool ldimm_mode) :
             insn_t(bits), p(pr), vloop_continue(false), fimap(f),
             cached_rd(0xff), cached_rs1(0xff),
             cached_rs2(0xff), cached_rs3(0xff),
@@ -29,7 +30,8 @@ public:
             offs_rs2(0), offs_rs3(0),
             new_offs_rd(0), new_offs_rs1(0),
             new_offs_rs2(0), new_offs_rs3(0),
-            prd(p_rd), prs1(p_rs1), prs2(p_rs2), prs3(p_rs3) {}
+            prd(p_rd), prs1(p_rs1), prs2(p_rs2), prs3(p_rs3),
+            ldst_imm_mode(ldimm_mode) {}
   uint64_t rd () { return predicated(_rd (), offs_rd , prd); }
   uint64_t rs1() { return predicated(_rs1(), offs_rs1, prs1); }
   uint64_t rs2() { return predicated(_rs2(), offs_rs2, prs2); }
@@ -38,6 +40,7 @@ public:
   uint64_t rvc_rs1s() { return predicated(_rvc_rs1s(), offs_rs1, prs1); }
   uint64_t rvc_rs2 () { return predicated(_rvc_rs2 (), offs_rs2, prs2); }
   uint64_t rvc_rs2s() { return predicated(_rvc_rs2s(), offs_rs2, prs2); }
+  uint64_t i_imm();
 
   uint64_t _rd () { return _remap(insn_t::rd (), fimap & REG_RD ,
                                   offs_rd , cached_rd, new_offs_rd); }
@@ -96,6 +99,7 @@ private:
   uint64_t &prs1;
   uint64_t &prs2;
   uint64_t &prs3;
+  bool ldst_imm_mode;
 
   // remaps the register through the lookup table.
   // will need to take the current loop index/offset somehow