From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 18 Feb 2022 21:01:11 +0000 (+0000)
Subject: add FPGA argument to DDR3SoC
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8796874b70831ccaa7c0f4945b74cdf5fef3db81;p=ls2.git

add FPGA argument to DDR3SoC
---

diff --git a/src/ls2.py b/src/ls2.py
index 54d4f4d..7fe9ca3 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -297,7 +297,7 @@ if __name__ == "__main__":
                                          "odt":4, "ras":4, "cas":4, "we":4})
 
     # set up the SOC
-    soc = DDR3SoC(dram_cls,
+    soc = DDR3SoC(fpga, dram_cls,
                   ddrphy_addr=0xff000000, # DRAM firmware init base
                   dramcore_addr=0x80000000,
                   ddr_addr=0x10000000,