From: Robert Jordens Date: Sun, 5 Apr 2015 09:49:06 +0000 (-0600) Subject: decorators: fix stacklevel, export in std X-Git-Tag: 24jan2021_ls180~2099^2~124 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8798ee8d73757ff6935739eb9dbf078b54238955;p=litex.git decorators: fix stacklevel, export in std --- diff --git a/migen/fhdl/decorators.py b/migen/fhdl/decorators.py index 62cda094..ddd1a965 100644 --- a/migen/fhdl/decorators.py +++ b/migen/fhdl/decorators.py @@ -48,11 +48,11 @@ class ModuleTransformer: @classmethod def adhoc(cls, i, *args, **kwargs): - warnings.warn("deprecated, use the plain transformer", DeprecationWarning) + warnings.warn("deprecated, use the plain transformer", DeprecationWarning, 2) return cls(*args, **kwargs)(i) def DecorateModule(transformer, *args, **kwargs): - warnings.warn("deprecated, use the plain transformer", DeprecationWarning) + warnings.warn("deprecated, use the plain transformer", DeprecationWarning, 2) return transformer.__self__(*args, **kwargs) class ControlInserter(ModuleTransformer): diff --git a/migen/fhdl/std.py b/migen/fhdl/std.py index 56bd97bc..a9ac658d 100644 --- a/migen/fhdl/std.py +++ b/migen/fhdl/std.py @@ -3,3 +3,5 @@ from migen.fhdl.module import Module, FinalizeError from migen.fhdl.specials import TSTriple, Instance, Memory from migen.fhdl.bitcontainer import log2_int, bits_for, flen, fiter, fslice, freversed from migen.fhdl.decorators import DecorateModule, InsertCE, InsertReset, RenameClockDomains +from migen.fhdl.decorators import (CEInserter, ResetInserter, + ClockDomainsRenamer, ModuleTransformer)