From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 11 Oct 2022 16:09:08 +0000 (+0100)
Subject: add asciidump option to Mem class
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=879a2eea16c06c4a5353a1cae604b1d92215a9a9;p=openpower-isa.git

add asciidump option to Mem class
---

diff --git a/src/openpower/decoder/isa/mem.py b/src/openpower/decoder/isa/mem.py
index 9132c357..87453ceb 100644
--- a/src/openpower/decoder/isa/mem.py
+++ b/src/openpower/decoder/isa/mem.py
@@ -141,7 +141,7 @@ class Mem:
         log("memassign", addr, sz, val)
         self.st(addr.value, val.value, sz, swap=False)
 
-    def dump(self, printout=True):
+    def dump(self, printout=True, asciidump=False):
         keys = list(self.mem.keys())
         keys.sort()
         res = []
@@ -149,7 +149,15 @@ class Mem:
             res.append(((k*8), self.mem[k]))
             if not printout:
                 continue
-            print ("%016x: %016x" % ((k*8) & 0xffffffffffffffff, self.mem[k]))
+            s = ""
+            if asciidump:
+                for i in range(8):
+                    c = chr(self.mem[k]>>(i*8) & 0xff)
+                    if not c.isprintable():
+                        c = "."
+                    s += c
+            print ("%016x: %016x" % ((k*8) & 0xffffffffffffffff,
+                                     self.mem[k]), s)
         return res
 
     def log_fancy(self, *, kind=LogKind.Default, name="Memory",