From: Maciej W. Rozycki <macro@wdc.com>
Date: Thu, 2 Apr 2020 14:43:05 +0000 (+0100)
Subject: doc: RISC-V: Update binutils requirement to 2.30
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=879bc686a0aac4277532fc2aa18704c125fb0c45;p=gcc.git

doc: RISC-V: Update binutils requirement to 2.30

Complement commit bfe78b08471f ("RISC-V: Using fmv.x.w/fmv.w.x rather
than fmv.x.s/fmv.s.x") and document a binutils 2.30 requirement in the
installation manual, matching the addition of fmv.x.w/fmv.w.x mnemonics
to GAS.

	gcc/
	* doc/install.texi (Specific) <riscv32-*-elf, riscv32-*-linux>
	<riscv64-*-elf, riscv64-*-linux>: Update binutils requirement to
	2.30.
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f0a9509d970..671411e5db3 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2020-04-02  Maciej W. Rozycki  <macro@wdc.com>
+
+	* doc/install.texi (Specific) <riscv32-*-elf, riscv32-*-linux>
+	<riscv64-*-elf, riscv64-*-linux>: Update binutils requirement to
+	2.30.
+
 2020-04-02  Kewen Lin  <linkw@gcc.gnu.org>
 
 	PR tree-optimization/94401
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 559610802be..bc5259d74c5 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -4545,8 +4545,7 @@ This configuration is intended for embedded systems.
 @heading riscv32-*-elf
 The RISC-V RV32 instruction set.
 This configuration is intended for embedded systems.
-This (and all other RISC-V) targets are supported upstream as of the
-binutils 2.28 release.
+This (and all other RISC-V) targets require the binutils 2.30 release.
 
 @html
 <hr />
@@ -4554,8 +4553,7 @@ binutils 2.28 release.
 @anchor{riscv32-x-linux}
 @heading riscv32-*-linux
 The RISC-V RV32 instruction set running GNU/Linux.
-This (and all other RISC-V) targets are supported upstream as of the
-binutils 2.28 release.
+This (and all other RISC-V) targets require the binutils 2.30 release.
 
 @html
 <hr />
@@ -4564,8 +4562,7 @@ binutils 2.28 release.
 @heading riscv64-*-elf
 The RISC-V RV64 instruction set.
 This configuration is intended for embedded systems.
-This (and all other RISC-V) targets are supported upstream as of the
-binutils 2.28 release.
+This (and all other RISC-V) targets require the binutils 2.30 release.
 
 @html
 <hr />
@@ -4573,8 +4570,7 @@ binutils 2.28 release.
 @anchor{riscv64-x-linux}
 @heading riscv64-*-linux
 The RISC-V RV64 instruction set running GNU/Linux.
-This (and all other RISC-V) targets are supported upstream as of the
-binutils 2.28 release.
+This (and all other RISC-V) targets require the binutils 2.30 release.
 
 @html
 <hr />