From: Gabe Black <gabeblack@google.com>
Date: Mon, 13 Apr 2020 04:58:55 +0000 (-0700)
Subject: x86: Use the common pseudoInst dispatch function.
X-Git-Tag: develop-gem5-snapshot~705
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=87baeab20fdba0fc5a29b9db744bc377858e3228;p=gem5.git

x86: Use the common pseudoInst dispatch function.

Instead of hand invoking each individual pseudo inst. New instructions
added in the future will automatically become available without a lot of
extra hand implementation. It also simplifies the x86 ISA description.

Change-Id: Ibb671dc2656e61679b7ed016c51a6c879e12910a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27789
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index e8b1e3d76..2236c4f85 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -144,98 +144,13 @@
             // to play with so there can be quite a few pseudo
             // instructions.
             //0x04: loadall_or_reset_or_hang();
-            0x4: decode IMMEDIATE {
-                format BasicOperate {
-                    0x00: m5arm({{
-                        PseudoInst::arm(xc->tcBase());
-                    }}, IsNonSpeculative);
-                    0x01: m5quiesce({{
-                        PseudoInst::quiesce(xc->tcBase());
-                    }}, IsNonSpeculative, IsQuiesce);
-                    0x02: m5quiesceNs({{
-                        PseudoInst::quiesceNs(xc->tcBase(), Rdi);
-                    }}, IsNonSpeculative, IsQuiesce);
-                    0x03: m5quiesceCycle({{
-                        PseudoInst::quiesceCycles(xc->tcBase(), Rdi);
-                    }}, IsNonSpeculative, IsQuiesce);
-                    0x04: m5quiesceTime({{
-                        Rax = PseudoInst::quiesceTime(xc->tcBase());
-                    }}, IsNonSpeculative);
-                    0x07: m5rpns({{
-                        Rax = PseudoInst::rpns(xc->tcBase());
-                    }}, IsNonSpeculative);
-                    0x21: m5exit({{
-                        PseudoInst::m5exit(xc->tcBase(), Rdi);
-                    }}, IsNonSpeculative);
-                    0x22: m5fail({{
-                        PseudoInst::m5fail(xc->tcBase(), Rdi, Rsi);
-                    }}, IsNonSpeculative);
-                    0x23: m5sum({{
-                        Rax = PseudoInst::m5sum(xc->tcBase(),
-                                Rdi, Rsi, Rdx, Rcx, R8, R9);
-                    }}, IsNonSpeculative);
-                    0x30: m5initparam({{
-                        Rax = PseudoInst::initParam(xc->tcBase(), Rdi, Rsi);
-                    }}, IsNonSpeculative);
-                    0x31: m5loadsymbol({{
-                        PseudoInst::loadsymbol(xc->tcBase());
-                    }}, IsNonSpeculative);
-                    0x40: m5resetstats({{
-                        PseudoInst::resetstats(xc->tcBase(), Rdi, Rsi);
-                    }}, IsNonSpeculative);
-                    0x41: m5dumpstats({{
-                        PseudoInst::dumpstats(xc->tcBase(), Rdi, Rsi);
-                    }}, IsNonSpeculative);
-                    0x42: m5dumpresetstats({{
-                        PseudoInst::dumpresetstats(xc->tcBase(), Rdi, Rsi);
-                    }}, IsNonSpeculative);
-                    0x43: m5checkpoint({{
-                        PseudoInst::m5checkpoint(xc->tcBase(), Rdi, Rsi);
-                    }}, IsNonSpeculative);
-                    0x50: m5readfile({{
-                        Rax = PseudoInst::readfile(
-                            xc->tcBase(), Rdi, Rsi, Rdx);
-                    }}, IsNonSpeculative);
-                    0x51: m5debugbreak({{
-                        PseudoInst::debugbreak(xc->tcBase());
-                    }}, IsNonSpeculative);
-                    0x52: m5switchcpu({{
-                        PseudoInst::switchcpu(xc->tcBase());
-                    }}, IsNonSpeculative);
-                    0x53: m5addsymbol({{
-                        PseudoInst::addsymbol(xc->tcBase(), Rdi, Rsi);
-                    }}, IsNonSpeculative);
-                    0x54: m5panic({{
-                        panic("M5 panic instruction called at pc = %#x.\n",
-                              RIP);
-                    }}, IsNonSpeculative);
-                    0x55: m5reserved1({{
-                        warn("M5 reserved opcode 1 ignored.\n");
-                    }}, IsNonSpeculative);
-                    0x56: m5reserved2({{
-                        warn("M5 reserved opcode 2 ignored.\n");
-                    }}, IsNonSpeculative);
-                    0x57: m5reserved3({{
-                        warn("M5 reserved opcode 3 ignored.\n");
-                    }}, IsNonSpeculative);
-                    0x58: m5reserved4({{
-                        warn("M5 reserved opcode 4 ignored.\n");
-                    }}, IsNonSpeculative);
-                    0x59: m5reserved5({{
-                        warn("M5 reserved opcode 5 ignored.\n");
-                    }}, IsNonSpeculative);
-                    0x5a: m5_work_begin({{
-                        PseudoInst::workbegin(xc->tcBase(), Rdi, Rsi);
-                    }}, IsNonSpeculative);
-                    0x5b: m5_work_end({{
-                        PseudoInst::workend(xc->tcBase(), Rdi, Rsi);
-                    }}, IsNonSpeculative);
-                    0x62: m5togglesync({{
-                        PseudoInst::togglesync(xc->tcBase());
-                    }}, IsNonSpeculative, IsQuiesce);
-                    default: Inst::UD2();
-                }
-            }
+            0x4: BasicOperate::gem5Op({{
+                uint64_t ret;
+                bool recognized = PseudoInst::pseudoInst<X86PseudoInstABI>(
+                        xc->tcBase(), IMMEDIATE, ret);
+                if (!recognized)
+                    fault = std::make_shared<InvalidOpcode>();
+            }}, IsNonSpeculative);
             0x05: decode FullSystemInt {
                 0: SyscallInst::syscall({{
                     return std::make_shared<SESyscallFault>();
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index 65b304f4e..d2098c3e9 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -112,6 +112,7 @@ output exec {{
 #include "arch/x86/cpuid.hh"
 #include "arch/x86/faults.hh"
 #include "arch/x86/memhelpers.hh"
+#include "arch/x86/pseudo_inst_abi.hh"
 #include "arch/x86/tlb.hh"
 #include "base/compiler.hh"
 #include "base/condcodes.hh"