From: Jakub Jelinek Date: Thu, 13 Dec 2018 07:58:42 +0000 (+0100) Subject: re PR target/88461 (AVX512: gcc should keep value in kN registers if possible) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=87d570a02295ac9391a17d6bb4e4a1d226a0af1b;p=gcc.git re PR target/88461 (AVX512: gcc should keep value in kN registers if possible) PR target/88461 * config/i386/i386.md (*zero_extendsidi2, zero_extenddi2, *zero_extendsi2, *zero_extendqihi2): Add =*k, *km alternatives. From-SVN: r267076 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index bce500dcdde..4e96dd061ca 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2018-12-13 Jakub Jelinek + + PR target/88461 + * config/i386/i386.md (*zero_extendsidi2, zero_extenddi2, + *zero_extendsi2, *zero_extendqihi2): Add =*k, *km alternatives. + 2018-12-12 Tom de Vries Jakub Jelinek diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 800b64917dc..a220346a068 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -3751,10 +3751,10 @@ (define_insn "*zero_extendsidi2" [(set (match_operand:DI 0 "nonimmediate_operand" - "=r,?r,?o,r ,o,?*y,?!*y,$r,$v,$x,*x,*v,*r") + "=r,?r,?o,r ,o,?*y,?!*y,$r,$v,$x,*x,*v,*r,*k") (zero_extend:DI (match_operand:SI 1 "x86_64_zext_operand" - "0 ,rm,r ,rmWz,0,r ,m ,v ,r ,m ,*x,*v,*k")))] + "0 ,rm,r ,rmWz,0,r ,m ,v ,r ,m ,*x,*v,*k,*km")))] "" { switch (get_attr_type (insn)) @@ -3806,6 +3806,8 @@ (const_string "avx512f") (eq_attr "alternative" "12") (const_string "x64_avx512bw") + (eq_attr "alternative" "13") + (const_string "avx512bw") ] (const_string "*"))) (set (attr "type") @@ -3819,7 +3821,7 @@ (const_string "multi")) (eq_attr "alternative" "8,9,10,11") (const_string "ssemov") - (eq_attr "alternative" "12") + (eq_attr "alternative" "12,13") (const_string "mskmov") ] (const_string "imovx"))) @@ -3881,16 +3883,17 @@ [(QI "avx512dq") (HI "avx512f") (SI "avx512bw") (DI "avx512bw")]) (define_insn "zero_extenddi2" - [(set (match_operand:DI 0 "register_operand" "=r,*r") + [(set (match_operand:DI 0 "register_operand" "=r,*r,*k") (zero_extend:DI - (match_operand:SWI12 1 "nonimmediate_operand" "m,*k")))] + (match_operand:SWI12 1 "nonimmediate_operand" "m,*k,*km")))] "TARGET_64BIT" "@ movz{l|x}\t{%1, %k0|%k0, %1} + kmov\t{%1, %k0|%k0, %1} kmov\t{%1, %k0|%k0, %1}" - [(set_attr "isa" "*,") - (set_attr "type" "imovx,mskmov") - (set_attr "mode" "SI,")]) + [(set_attr "isa" "*,,") + (set_attr "type" "imovx,mskmov,mskmov") + (set_attr "mode" "SI,,")]) (define_expand "zero_extendsi2" [(set (match_operand:SI 0 "register_operand") @@ -3933,16 +3936,17 @@ (set_attr "mode" "SI")]) (define_insn "*zero_extendsi2" - [(set (match_operand:SI 0 "register_operand" "=r,*r") + [(set (match_operand:SI 0 "register_operand" "=r,*r,*k") (zero_extend:SI - (match_operand:SWI12 1 "nonimmediate_operand" "m,*k")))] + (match_operand:SWI12 1 "nonimmediate_operand" "m,*k,*km")))] "!(TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))" "@ movz{l|x}\t{%1, %0|%0, %1} + kmov\t{%1, %0|%0, %1} kmov\t{%1, %0|%0, %1}" - [(set_attr "isa" "*,") - (set_attr "type" "imovx,mskmov") - (set_attr "mode" "SI,")]) + [(set_attr "isa" "*,,") + (set_attr "type" "imovx,mskmov,mskmov") + (set_attr "mode" "SI,,")]) (define_expand "zero_extendqihi2" [(set (match_operand:HI 0 "register_operand") @@ -3985,15 +3989,16 @@ ; zero extend to SImode to avoid partial register stalls (define_insn "*zero_extendqihi2" - [(set (match_operand:HI 0 "register_operand" "=r,*r") - (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,*k")))] + [(set (match_operand:HI 0 "register_operand" "=r,*r,*k") + (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,*k,*km")))] "!(TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))" "@ movz{bl|x}\t{%1, %k0|%k0, %1} - kmovb\t{%1, %k0|%k0, %1}" - [(set_attr "isa" "*,avx512dq") - (set_attr "type" "imovx,mskmov") - (set_attr "mode" "SI,QI")]) + kmovb\t{%1, %k0|%k0, %1} + kmovb\t{%1, %0|%0, %1}" + [(set_attr "isa" "*,avx512dq,avx512dq") + (set_attr "type" "imovx,mskmov,mskmov") + (set_attr "mode" "SI,QI,QI")]) (define_insn_and_split "*zext_doubleword_and" [(set (match_operand:DI 0 "register_operand" "=&")