From: lkcl Date: Wed, 16 Dec 2020 17:16:06 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~1268 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=87d64711da9ff722536f27f2b1f59117e8bffb3b;p=libreriscv.git --- diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index 775eae2ce..aaf09cef8 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -12,7 +12,7 @@ counting up as you move to the LSB end). All bit ranges are inclusive (so 64-bit instructions are split into two 32-bit words, the prefix and the suffix. The prefix always comes before the suffix in PC order. -SVP64 is designed so that when the prefix is all zeros, no effect or influence occurs (no augmentation) such that all standard OpenPOWER v3.B instructions may be active at that time, in full. The corollary is that when the SV prefix is nonzero, alternative meanings may be given to all and any instructions. +SVP64 is designed so that when the prefix is all zeros, no effect or influence occurs (no augmentation) such that all standard OpenPOWER v3.B instructions may be active at that time, in full (and SV is quiescent). The corollary is that when the SV prefix is nonzero, alternative meanings may be given to all and any instructions. ## Definition of Reserved in this spec.