From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 20 Feb 2022 22:09:42 +0000 (+0000)
Subject: separate out shiftrot stages due to size of main stage being so large
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=87d6b84e96fb62cda16cc9f335e34fe15ad6cd97;p=soc.git

separate out shiftrot stages due to size of main stage being so large
---

diff --git a/src/soc/fu/shift_rot/pipeline.py b/src/soc/fu/shift_rot/pipeline.py
index 80e46038..67dc034c 100644
--- a/src/soc/fu/shift_rot/pipeline.py
+++ b/src/soc/fu/shift_rot/pipeline.py
@@ -4,11 +4,15 @@ from soc.fu.shift_rot.input_stage import ShiftRotInputStage
 from soc.fu.shift_rot.main_stage import ShiftRotMainStage
 from soc.fu.shift_rot.output_stage import ShiftRotOutputStage
 
-class ShiftRotStages(PipeModBaseChain):
+class ShiftRotStart(PipeModBaseChain):
     def get_chain(self):
         inp = ShiftRotInputStage(self.pspec)
+        return [inp]
+
+class ShiftRotStage(PipeModBaseChain):
+    def get_chain(self):
         main = ShiftRotMainStage(self.pspec)
-        return [inp, main]
+        return [main]
 
 
 class ShiftRotStageEnd(PipeModBaseChain):
@@ -21,13 +25,15 @@ class ShiftRotBasePipe(ControlBase):
     def __init__(self, pspec):
         ControlBase.__init__(self)
         self.pspec = pspec
-        self.pipe1 = ShiftRotStages(pspec)
-        self.pipe2 = ShiftRotStageEnd(pspec)
-        self._eqs = self.connect([self.pipe1, self.pipe2])
+        self.pipe1 = ShiftRotStart(pspec)
+        self.pipe2 = ShiftRotStage(pspec)
+        self.pipe3 = ShiftRotStageEnd(pspec)
+        self._eqs = self.connect([self.pipe1, self.pipe2, self.pipe3])
 
     def elaborate(self, platform):
         m = ControlBase.elaborate(self, platform)
         m.submodules.pipe1 = self.pipe1
         m.submodules.pipe2 = self.pipe2
+        m.submodules.pipe3 = self.pipe3
         m.d.comb += self._eqs
         return m