From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 19 Aug 2020 18:02:30 +0000 (+0100)
Subject: more subtle interactions between wishbone bus when there are delays,
X-Git-Tag: semi_working_ecp5~290
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=87dc5a797a885c0e5aa583359c837565c322c9d6;p=soc.git

more subtle interactions between wishbone bus when there are delays,
LD/ST CompUnit and PortInterface
---

diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py
index 7606ade5..5109ad25 100644
--- a/src/soc/experiment/compldst_multi.py
+++ b/src/soc/experiment/compldst_multi.py
@@ -454,7 +454,8 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         comb += wr_reset.eq(rst_l.q & busy_o & self.shadown_i &
                             ~(self.st.rel_o | self.wr.rel_o[0] |
                               self.wr.rel_o[1]) &
-                            (lod_l.qn | op_is_st))
+                            (lod_l.qn | op_is_st) &
+                            (~self.pi.busy_o | op_is_ld))
         comb += self.done_o.eq(wr_reset)
 
         ######################
diff --git a/src/soc/experiment/pi2ls.py b/src/soc/experiment/pi2ls.py
index 501eb55c..3964122b 100644
--- a/src/soc/experiment/pi2ls.py
+++ b/src/soc/experiment/pi2ls.py
@@ -30,6 +30,8 @@ from nmigen.utils import log2_int
 
 from nmigen import Elaboratable, Module, Signal
 from nmutil.latch import SRLatch
+from nmutil.util import rising_edge
+
 
 
 class Pi2LSUI(PortInterfaceBase):
@@ -56,7 +58,7 @@ class Pi2LSUI(PortInterfaceBase):
 
     def set_wr_data(self, m, data, wen):  # mask already done in addr setup
         m.d.comb += self.lsui.x_st_data_i.eq(data)
-        return (~self.lsui_busy)
+        return (~(self.lsui.x_busy_o | self.lsui_busy))
 
     def get_rd_data(self, m):
         return self.lsui.m_ld_data_o, ~self.lsui_busy
@@ -94,15 +96,17 @@ class Pi2LSUI(PortInterfaceBase):
                     m.next = "WAITDEASSERT"
             with m.State("WAITDEASSERT"):
                 # when no longer busy: back to start
-                with m.If(~self.valid_l.q):
+                with m.If(~pi.is_st_i & ~pi.busy_o):
                     m.next = "IDLE"
 
         # indicate valid at both ends. OR with lsui_busy (stops comb loop)
-        m.d.comb += self.lsui.m_valid_i.eq(self.valid_l.q | self.lsui_busy)
-        m.d.comb += self.lsui.x_valid_i.eq(self.valid_l.q | self.lsui_busy)
+        m.d.comb += self.lsui.m_valid_i.eq(self.valid_l.q )
+        m.d.comb += self.lsui.x_valid_i.eq(self.valid_l.q )
 
         # reset the valid latch when not busy.  sync to stop loop
-        m.d.sync += self.valid_l.r.eq(~self.lsui_busy)
+        lsui_active = Signal()
+        m.d.comb += lsui_active.eq(~self.lsui.x_busy_o)
+        m.d.comb += self.valid_l.r.eq(rising_edge(m, lsui_active))
 
         return m
 
diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index 492b7c2e..6361f456 100644
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -167,7 +167,10 @@ class PortInterfaceBase(Elaboratable):
         m.submodules.adrok_l = adrok_l = SRLatch(False, name="addr_acked")
         m.submodules.busy_l = busy_l = SRLatch(False, name="busy")
         m.submodules.cyc_l = cyc_l = SRLatch(True, name="cyc")
-        comb += st_done.s.eq(0)
+
+        self.busy_l = busy_l
+
+        sync += st_done.s.eq(0)
         comb += st_done.r.eq(0)
         comb += st_active.r.eq(0)
         comb += ld_active.r.eq(0)
@@ -250,7 +253,7 @@ class PortInterfaceBase(Elaboratable):
             # TODO: replace with link to LoadStoreUnitInterface.x_store_data
             # and also handle the ready/stall/busy protocol
             stok = self.set_wr_data(m, stdata, lenexp.lexp_o)
-            comb += st_done.s.eq(1)     # store done trigger
+            sync += st_done.s.eq(1)     # store done trigger
         with m.If(st_done.q):
             comb += reset_l.s.eq(stok)   # reset mode after 1 cycle