From: lkcl Date: Fri, 18 Dec 2020 04:35:05 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~1221 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=87deae0c23813a2038972f03992a389d9c3d6da2;p=libreriscv.git --- diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index e07b70517..72d387f78 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -144,7 +144,7 @@ RM-2P-2S1D: Note that for 1S2P the EXTRA2 dest and src names are switched (Rsrc_EXTRA2 is in bits 8:9, Rdest1_EXTRA2 in 10:11) -Note also that LD with update indexed, which takes 2 src and 2 dest (e.g. `lhaux RT,RA,RB`), does not have room for 4 registers and also Twin Prefication. therefore these are treated as RM-2P-2S1D and the src spec for RA is also used for the same RA as a dest. +Note also that LD with update indexed, which takes 2 src and 2 dest (e.g. `lhaux RT,RA,RB`), does not have room for 4 registers and also Twin Predication. therefore these are treated as RM-2P-2S1D and the src spec for RA is also used for the same RA as a dest. ## R\*_EXTRA2 and R\*_EXTRA3 Encoding