From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 13 Feb 2019 18:44:52 +0000 (-0800)
Subject: Rip out some more stuff
X-Git-Tag: working-ls180~1237^2~342
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=87f059adf7c075cc5dfe2e01b674fffa567db425;p=yosys.git

Rip out some more stuff
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 19b94641b..65eafffd9 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -67,38 +67,6 @@ extern "C" int Abc_RealMain(int argc, char *argv[]);
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-enum class gate_type_t {
-	G_NONE,
-	G_FF,
-	G_BUF,
-	G_NOT,
-	G_AND,
-	G_NAND,
-	G_OR,
-	G_NOR,
-	G_XOR,
-	G_XNOR,
-	G_ANDNOT,
-	G_ORNOT,
-	G_MUX,
-	G_AOI3,
-	G_OAI3,
-	G_AOI4,
-	G_OAI4
-};
-
-#define G(_name) gate_type_t::G_ ## _name
-
-struct gate_t
-{
-	int id;
-	gate_type_t type;
-	int in1, in2, in3, in4;
-	bool is_port;
-	RTLIL::SigBit bit;
-	RTLIL::State init;
-};
-
 bool map_mux4;
 bool map_mux8;
 bool map_mux16;
@@ -107,7 +75,6 @@ bool markgroups;
 int map_autoidx;
 SigMap assign_map;
 RTLIL::Module *module;
-std::vector<gate_t> signal_list;
 std::map<RTLIL::SigBit, int> signal_map;
 std::map<RTLIL::SigBit, RTLIL::State> signal_init;
 pool<std::string> enabled_gates;
@@ -258,7 +225,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 	map_autoidx = autoidx++;
 
 	signal_map.clear();
-	signal_list.clear();
 	pi_map.clear();
 	po_map.clear();
 	recover_init = false;
@@ -959,7 +925,6 @@ struct Abc9Pass : public Pass {
 		log_push();
 
 		assign_map.clear();
-		signal_list.clear();
 		signal_map.clear();
 		signal_init.clear();
 		pi_map.clear();
@@ -1389,7 +1354,6 @@ struct Abc9Pass : public Pass {
 		}
 
 		assign_map.clear();
-		signal_list.clear();
 		signal_map.clear();
 		signal_init.clear();
 		pi_map.clear();