From: lkcl <lkcl@web>
Date: Thu, 31 Dec 2020 21:54:24 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~676
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=87f16984747c81bd2f9502d0407ffb4afa031b50;p=libreriscv.git

---

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index 633a5cd49..fae284f92 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -290,8 +290,9 @@ registers.  In c this would be:
 
 Conceptually, to get our variable element width vectors,
 we may think of the regfile as instead being the following c-based data
-structure, where all types uint16_t are in little-endian order:
+structure, where all types uint16_t etc. are in little-endian order:
 
+    #pragma(packed)
     typedef union {
         uint8_t  actual_bytes[8];
         uint8_t  b[0]; // array of type uint8_t