From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 15 Jan 2022 14:03:02 +0000 (+0000)
Subject: tidyup PortInterface
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=87f246e99057139624581590c154795950db6469;p=soc.git

tidyup PortInterface
---

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index 22788af2..6fe1e681 100644
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -97,9 +97,10 @@ class PortInterface(RecordObject):
 
         RecordObject.__init__(self, name=name)
 
-        # distinguish op type (ld/st)
+        # distinguish op type (ld/st/dcbz)
         self.is_ld_i    = Signal(reset_less=True)
         self.is_st_i    = Signal(reset_less=True)
+        self.is_dcbz_i     = Signal(reset_less=True) # cache-line zeroing
 
         # LD/ST data length (TODO: other things may be needed)
         self.data_len = Signal(4, reset_less=True)
@@ -125,8 +126,6 @@ class PortInterface(RecordObject):
         self.priv_mode  = Signal() # not ctrl.msr(MSR_PR);
         self.mode_32bit = Signal() # not ctrl.msr(MSR_SF);
 
-        self.is_dcbz_i     = Signal(reset_less=True)
-
         # mmu
         self.mmu_done          = Signal() # keep for now