From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 27 Sep 2020 21:23:26 +0000 (+0000)
Subject: Makefile add chip building
X-Git-Tag: partial-core-ls180-gdsii~71
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=87ffcf1fd12c5f0bbeb937bff8db23c39000c506;p=soclayout.git

Makefile add chip building
---

diff --git a/experiments9/Makefile b/experiments9/Makefile
index 3498fc5..d90a63b 100755
--- a/experiments9/Makefile
+++ b/experiments9/Makefile
@@ -3,8 +3,15 @@
        PHYSICAL_SYNTHESIS = Coriolis
                DESIGN_KIT = sxlib
 
-            YOSYS_SET_TOP = Yes
-            USE_CLOCKTREE = No
+#            YOSYS_SET_TOP = Yes
+                    CHIP  = chip
+                    CORE  = ls180
+                   MARGIN = 2
+                   BOOMOPT =
+                   BOOGOPT =
+                   LOONOPT =
+                   NSL2VHOPT = -vasy # -split -p
+            USE_CLOCKTREE = Yes
                 USE_DEBUG = No
                  USE_KITE = No
                 VST_FLAGS = --vst-use-concat
@@ -23,10 +30,17 @@ pinmux:
 blif:      ls180.blif
 vst:       ls180.vst
 
-layout:    ls180_r.ap
-gds:       ls180_r.gds
+lvx:       lvx-chip_cts_r
+druc:      druc-chip_cts_r
+dreal:     dreal-chip_cts_r
+flatph:     flatph-chip_cts_r
+view:      cgt-chip_cts_r
 
-lvx:       lvx-ls180_r
-druc:      druc-ls180_r
-view:      cgt-ls180_r
-viewn:     cgt-ls180
+layout:    chip_cts_r.ap
+gds:       chip_cts_r.gds
+gds_flat:  chip_cts_r_flat.gds
+cif:  	   chip_cts_r.cif
+
+
+view:      cgt-chip_cts_r
+sim:       asimut-ls180_cts_r