From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 20 Feb 2020 20:34:28 +0000 (+0000)
Subject: change name to not clash with cell name add1
X-Git-Tag: ls180-24jan2020~136
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=881d9f14be2bc15d5102064054dd4e58063cc8e6;p=ieee754fpu.git

change name to not clash with cell name add1
---

diff --git a/src/ieee754/part/partsig.py b/src/ieee754/part/partsig.py
index bf0e85bc..75417cfd 100644
--- a/src/ieee754/part/partsig.py
+++ b/src/ieee754/part/partsig.py
@@ -51,7 +51,7 @@ class PartitionedSignal:
 
     def get_modname(self, category):
         self.modnames[category] += 1
-        return "%s%d" % (category, self.modnames[category])
+        return "%s_%d" % (category, self.modnames[category])
 
     def eq(self, val):
         return self.sig.eq(getsig(val))