From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 15 Feb 2015 12:00:00 +0000 (+0100)
Subject: Added final checks to "synth" and "synth_xilinx"
X-Git-Tag: yosys-0.6~429
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=881dcd8af988664b92a85daa5d82e90b1df29b51;p=yosys.git

Added final checks to "synth" and "synth_xilinx"
---

diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index a50db53ee..56ab6eaff 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -90,12 +90,14 @@ struct SynthPass : public Pass {
 		log("        techmap\n");
 		log("        opt -fast\n");
 	#ifdef YOSYS_ENABLE_ABC
-		log("\n");
-		log("    abc:\n");
 		log("        abc -fast\n");
 		log("        opt -fast\n");
 	#endif
 		log("\n");
+		log("    check:\n");
+		log("        hierarchy -check\n");
+		log("        check\n");
+		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
@@ -172,15 +174,20 @@ struct SynthPass : public Pass {
 			Pass::call(design, "opt -full");
 			Pass::call(design, "techmap");
 			Pass::call(design, "opt -fast");
+
+			if (!noabc) {
+		#ifdef YOSYS_ENABLE_ABC
+				Pass::call(design, "abc -fast");
+				Pass::call(design, "opt -fast");
+		#endif
+			}
 		}
 
-	#ifdef YOSYS_ENABLE_ABC
-		if (check_label(active, run_from, run_to, "abc") && !noabc)
+		if (check_label(active, run_from, run_to, "check"))
 		{
-			Pass::call(design, "abc -fast");
-			Pass::call(design, "opt -fast");
+			Pass::call(design, "hierarchy -check");
+			Pass::call(design, "check");
 		}
-	#endif
 
 		log_pop();
 	}
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 7812fa290..02207593a 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -98,6 +98,10 @@ struct SynthXilinxPass : public Pass {
 		log("        techmap -map +/xilinx/cells_map.v\n");
 		log("        clean\n");
 		log("\n");
+		log("    check:\n");
+		log("        hierarchy -check\n");
+		log("        check -noinit\n");
+		log("\n");
 		log("    edif:\n");
 		log("        write_edif synth.edif\n");
 		log("\n");
@@ -195,6 +199,12 @@ struct SynthXilinxPass : public Pass {
 			Pass::call(design, "clean");
 		}
 
+		if (check_label(active, run_from, run_to, "check"))
+		{
+			Pass::call(design, "hierarchy -check");
+			Pass::call(design, "check -noinit");
+		}
+
 		if (check_label(active, run_from, run_to, "edif"))
 		{
 			if (!edif_file.empty())