From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 17 Apr 2018 06:17:46 +0000 (+0100)
Subject: add vector length pseudocode
X-Git-Tag: convert-csv-opcode-to-binary~5631
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=881f44ab4d4b665e9ad49a351e0f5b4a0e6ed93c;p=libreriscv.git

add vector length pseudocode
---

diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index a8bc2f170..ad2ced559 100644
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -422,11 +422,12 @@ Pseudo-code (excludes CSR SIMD bitwidth):
           vreg[rd+j][i] = mem[sreg[base] + offs + j*stride];
         }
 
-Taking CSR (SIMD) bitwidth into account involves extending vl according
-to the "Bitwidth Virtual Register Reordering" scheme shown in the Appendix.
+Taking CSR (SIMD) bitwidth into account involves using the vector
+length and register encoding according to the "Bitwidth Virtual Register
+Reordering" scheme shown in the Appendix (see function "regoffs").
 
 A similar instruction exists for STORE, with identical topological
-translation of all features.
+translation of all features.  **TODO**
 
 # Note on implementation of parallelism