From: lkcl <lkcl@web>
Date: Sun, 15 Oct 2023 17:19:16 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8822beb27787a0627fa09953edea30b2c0f00a3b;p=libreriscv.git

---

diff --git a/simple_v_extension/daxpy_example.mdwn b/simple_v_extension/daxpy_example.mdwn
index 86b2fc2ca..55c49863b 100644
--- a/simple_v_extension/daxpy_example.mdwn
+++ b/simple_v_extension/daxpy_example.mdwn
@@ -2,7 +2,15 @@
 
 This is a standard textbook algorithm demonstration for Vector and SIMD ISAs.
 
-<https://bugs.libre-soc.org/show_bug.cgi?id=1117>
+* <https://bugs.libre-soc.org/show_bug.cgi?id=1117>
+
+Summary
+
+| ISA | total | loop | words | notes |
+|-----|-------|------|-------|-------|
+| SVP64 | 8 | 6 | 13 | 5 64-bit, 4 32-bit |
+| RVV | 13 | 11 | 9.5 | 7 32-bit, 5 16-bit |
+| SVE | 12 | 7 | 12 | all 32-bit |
 
 # c code
 
@@ -13,14 +21,6 @@ This is a standard textbook algorithm demonstration for Vector and SIMD ISAs.
     }
 ```
 
-Summary
-
-| ISA | total | loop | words | notes |
-|-----|-------|------|-------|-------|
-| SVP64 | 8 | 6 | 13 | 5 64-bit, 4 32-bit |
-| RVV | 13 | 11 | 9.5 | 7 32-bit, 5 16-bit |
-| SVE | 12 | 7 | 12 | all 32-bit |
-
 # SVP64 Power ISA version
 
 The first instruction is simple: the plan is to use CTR for looping.