From: Cesar Strauss <cestrauss@gmail.com>
Date: Wed, 8 Jul 2020 09:42:07 +0000 (-0300)
Subject: Start the FSM-based ALU example.
X-Git-Tag: div_pipeline~161
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=883908820e005991336bcfd88fb9afd86f5fec0e;p=soc.git

Start the FSM-based ALU example.
---

diff --git a/src/soc/experiment/alu_fsm.py b/src/soc/experiment/alu_fsm.py
new file mode 100644
index 00000000..96290f4e
--- /dev/null
+++ b/src/soc/experiment/alu_fsm.py
@@ -0,0 +1,14 @@
+"""Simple example of a FSM-based ALU
+
+This demonstrates a design that follows the valid/ready protocol of the
+ALU, but with a FSM implementation, instead of a pipeline.
+
+The basic rules are:
+
+1) p.ready_o is asserted on the initial ("Idle") state, otherwise it keeps low.
+2) n.valid_o is asserted on the final ("Done") state, otherwise it keeps low.
+3) The FSM stays in the Idle state while p.valid_i is low, otherwise
+   it accepts the input data and moves on.
+4) The FSM stays in the Done state while n.ready_i is low, otherwise
+   it releases the output data and goes back to the Idle state.
+"""