From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 3 Jan 2007 05:52:30 +0000 (-0500)
Subject: Merge zizzer:/bk/newmem
X-Git-Tag: m5_2.0_beta3~255
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8840ebcb00f3988c781063e572b6df5742968f95;p=gem5.git

Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/newmem

--HG--
extra : convert_revision : f4a05accb8fa24d425dd818b1b7f268378180e99
---

8840ebcb00f3988c781063e572b6df5742968f95
diff --cc configs/example/fs.py
index d479d717e,5d7d49616..b878f2bd4
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@@ -1,4 -1,4 +1,4 @@@
--# Copyright (c) 2006 The Regents of The University of Michigan
++# Copyright (c) 2006-2007 The Regents of The University of Michigan
  # All rights reserved.
  #
  # Redistribution and use in source and binary forms, with or without
diff --cc src/arch/sparc/isa/decoder.isa
index e8578291c,e2bebd987..8abaf1007
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@@ -1,4 -1,4 +1,4 @@@
--// Copyright (c) 2006 The Regents of The University of Michigan
++// Copyright (c) 2006-2007 The Regents of The University of Michigan
  // All rights reserved.
  //
  // Redistribution and use in source and binary forms, with or without
diff --cc src/arch/sparc/isa/formats/mem/blockmem.isa
index c4f052f98,5d05dad03..62ac4b43a
--- a/src/arch/sparc/isa/formats/mem/blockmem.isa
+++ b/src/arch/sparc/isa/formats/mem/blockmem.isa
@@@ -1,4 -1,4 +1,4 @@@
--// Copyright (c) 2006 The Regents of The University of Michigan
++// Copyright (c) 2006-2007 The Regents of The University of Michigan
  // All rights reserved.
  //
  // Redistribution and use in source and binary forms, with or without
diff --cc src/arch/sparc/isa/formats/mem/util.isa
index c56821c4f,b6e0945b7..5bb4e1fe6
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@@ -1,4 -1,4 +1,4 @@@
--// Copyright (c) 2006 The Regents of The University of Michigan
++// Copyright (c) 2006-2007 The Regents of The University of Michigan
  // All rights reserved.
  //
  // Redistribution and use in source and binary forms, with or without
diff --cc src/cpu/exetrace.cc
index 98e75d83a,352a11958..378fcd09b
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@@ -391,24 -386,23 +392,31 @@@ Trace::InstRecord::dump(ostream &outs
                          diffPil = true;
                      if(shared_data->cwp != thread->readMiscReg(MISCREG_CWP))
                          diffCwp = true;
 -                    if(shared_data->cansave != thread->readMiscReg(MISCREG_CANSAVE))
 +                    //if(shared_data->cansave != thread->readMiscReg(MISCREG_CANSAVE))
 +                    if(shared_data->cansave !=
 +                            thread->readIntReg(NumIntArchRegs + 3))
                          diffCansave = true;
 +                    //if(shared_data->canrestore !=
 +                    //	    thread->readMiscReg(MISCREG_CANRESTORE))
                      if(shared_data->canrestore !=
 -                            thread->readMiscReg(MISCREG_CANRESTORE))
 +                            thread->readMiscReg(NumIntArchRegs + 4))
                          diffCanrestore = true;
 -                    if(shared_data->otherwin != thread->readMiscReg(MISCREG_OTHERWIN))
 +                    //if(shared_data->otherwin != thread->readMiscReg(MISCREG_OTHERWIN))
 +                    if(shared_data->otherwin !=
 +                            thread->readIntReg(NumIntArchRegs + 5))
                          diffOtherwin = true;
 -                    if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN))
 +                    //if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN))
 +                    if(shared_data->cleanwin !=
 +                            thread->readMiscReg(NumIntArchRegs + 6))
                          diffCleanwin = true;
  
+                     for (int i = 0; i < 64; i++) {
+                         if (shared_data->itb[i] !=  thread->getITBPtr()->TteRead(i))
+                                 diffTlb = true;
+                         if (shared_data->dtb[i] !=  thread->getDTBPtr()->TteRead(i))
+                                 diffTlb = true;
+                     }
+ 
                      if ((diffPC || diffCC || diffInst || diffRegs || diffTpc ||
                              diffTnpc || diffTstate || diffTt || diffHpstate ||
                              diffHtstate || diffHtba || diffPstate || diffY ||
diff --cc src/cpu/m5legion_interface.h
index bfb88485a,c3ba5986e..4cb270e66
--- a/src/cpu/m5legion_interface.h
+++ b/src/cpu/m5legion_interface.h
@@@ -1,5 -1,5 +1,5 @@@
  /*
-- * Copyright (c) 2006 The Regents of The University of Michigan
++ * Copyright (c) 2006-2007 The Regents of The University of Michigan
   * All rights reserved.
   *
   * Redistribution and use in source and binary forms, with or without
diff --cc src/unittest/Makefile
index 1f0584066,0c11b9563..e22b80b48
--- a/src/unittest/Makefile
+++ b/src/unittest/Makefile
@@@ -1,4 -1,4 +1,4 @@@
--# Copyright (c) 2006 The Regents of The University of Michigan
++# Copyright (c) 2006-2007 The Regents of The University of Michigan
  # All rights reserved.
  #
  # Redistribution and use in source and binary forms, with or without