From: Luke Kenneth Casson Leighton Date: Sun, 19 Jul 2020 19:51:40 +0000 (+0100) Subject: expose core_stop_i to outside as well X-Git-Tag: semi_working_ecp5~669 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=884d7f391f56d6f2131bb10a522799e71493e79d;p=soc.git expose core_stop_i to outside as well --- diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index b7c38887..59b463b0 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -49,6 +49,7 @@ class TestIssuer(Elaboratable): self.pc_o = Signal(64, reset_less=True) self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me" self.core_start_i = Signal() + self.core_stop_i = Signal() self.core_bigendian_i = Signal() self.busy_o = Signal(reset_less=True) self.halted_o = Signal(reset_less=True) @@ -74,6 +75,7 @@ class TestIssuer(Elaboratable): comb += self.busy_o.eq(core.busy_o) comb += self.halted_o.eq(core.core_terminated_o) comb += self.core_start_i.eq(core.core_start_i) + comb += self.core_stop_i.eq(core.core_stop_i) comb += self.core_bigendian_i.eq(core.bigendian_i) # temporary hack: says "go" immediately for both address gen and ST