From: Wesley W. Terpstra <wesley@sifive.com>
Date: Thu, 29 Jun 2017 20:41:30 +0000 (-0700)
Subject: mig: fix MemoryDevice to use 'reg' properly
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=886680af49a0b7e3e5acac2678d9c5a8da9b4a5f;hp=a8e20f447c64d485901b62b4dc48d4761fc9f09a;p=sifive-blocks.git

mig: fix MemoryDevice to use 'reg' properly
---

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
index 931e9be..f6ae153 100644
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
@@ -24,7 +24,7 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
   val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
     slaves = Seq(AXI4SlaveParameters(
       address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)),
-      resources     = device.reg("mem"),
+      resources     = device.reg,
       regionType    = RegionType.UNCACHED,
       executable    = true,
       supportsWrite = TransferSizes(1, 256*8),