From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sun, 25 Jan 2015 15:21:56 +0000 (+0100)
Subject: update LiteScope
X-Git-Tag: 24jan2021_ls180~2572^2~13
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8887bea721463c6a477aa70bc0923258936c5e4b;p=litex.git

update LiteScope
---

diff --git a/README b/README
index 901bb281..1080794c 100644
--- a/README
+++ b/README
@@ -12,7 +12,7 @@
 ---------
 LiteSATA provides a small footprint and configurable SATA gen1/2/3 core.
 
-LiteSATA is part of LiteX libraries whose aims is to lower entry level of complex
+LiteSATA is part of LiteX libraries whose aims are to lower entry level of complex
 FPGA IP cores by providing simple, elegant and efficient implementations of
 components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
 
diff --git a/targets/bist.py b/targets/bist.py
index 9d803149..118d3a1a 100644
--- a/targets/bist.py
+++ b/targets/bist.py
@@ -13,7 +13,7 @@ from misoclib import identifier
 from litescope.common import *
 from litescope.bridge.uart2wb import LiteScopeUART2WB
 from litescope.frontend.la import LiteScopeLA
-from litescope.core.trigger import LiteScopeTerm
+from litescope.core.port import LiteScopeTerm
 
 from litesata.common import *
 from litesata.phy import LiteSATAPHY
@@ -164,7 +164,7 @@ class BISTSoCDevel(BISTSoC, AutoCSR):
 		self.sata_core_command_rx_fsm_state = Signal(4)
 		self.sata_core_command_tx_fsm_state = Signal(4)
 
-		self.debug = (
+		debug = (
 			self.sata_phy.ctrl.ready,
 
 			self.sata_phy.source.stb,
@@ -201,8 +201,8 @@ class BISTSoCDevel(BISTSoC, AutoCSR):
 			self.sata_core_command_tx_fsm_state,
 		)
 
-		self.submodules.la = LiteScopeLA(2048, self.debug)
-		self.la.add_port(LiteScopeTerm)
+		self.submodules.la = LiteScopeLA(debug, 2048)
+		self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
 		atexit.register(self.exit, platform)
 
 	def do_finalize(self):
@@ -218,6 +218,6 @@ class BISTSoCDevel(BISTSoC, AutoCSR):
 
 	def exit(self, platform):
 		if platform.vns is not None:
-			self.la.export(self.debug, platform.vns, "./test/la.csv")
+			self.la.export(platform.vns, "../test/la.csv")
 
 default_subtarget = BISTSoC
diff --git a/test/test_la.py b/test/test_la.py
index 436bc9e2..66867c9b 100644
--- a/test/test_la.py
+++ b/test/test_la.py
@@ -44,19 +44,21 @@ conditions["rd_resp"] = {
 	"sata_command_rx_source_payload_read"	: 1,
 }
 
-la.prog_term(port=0, cond=conditions[trig])
-la.prog_sum("term")
+la.configure_term(port=0, cond=conditions[trig])
+la.configure_sum("term")
 
-# Trigger / wait / receive
-la.trigger(offset=64, length=1024)
+# Run Logic Analyzer
+la.run(offset=64, length=1024)
 
 #identify.run(blocking=False)
 generator.run(0, 2, 1, 0, blocking=False)
 #checker.run(0, 2, 1, 0, blocking=False)
-la.wait_done()
 
-la.read()
-la.export("dump.vcd")
+while not la.done():
+	pass
+
+la.upload()
+la.save("dump.vcd")
 ###
 wb.close()