From: lkcl <lkcl@web>
Date: Sun, 8 May 2022 21:52:05 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2295
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=88973c92a2d21a769ea61d0150c66c673d20bf9a;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 161c5511e..c81a50425 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -892,8 +892,8 @@ the computation. In this case, that's an expensive inconvenience.
 Vertical-First allows *scalar* temporary registers to be utilised
 in the assessment as to whether a particular Vector element should
 be skipped, utilising a straight Branch instruction.  This technique
-is pioneered by Mitch Alsup and is a key feature of his VVM Engine
-in MyISA 66000.  Careful analysis of the registers within the
+is pioneered by Mitch Alsup and is a key feature of his VVM Extension
+to MyISA 66000.  Careful analysis of the registers within the
 Vertical-First Loop allows a Multi-Issue Out-of-Order Engine to
 *amortise in-flight scalar looped operations into SIMD batches*
 as long as the loop is kept small enough to entirely fit into