From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 21 Apr 2020 14:14:34 +0000 (+0000)
Subject: squeeze size a bit more
X-Git-Tag: partial-core-ls180-gdsii~137
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=889a9e87b699aff27523a43e5f8ab65998bfe1cd;p=soclayout.git

squeeze size a bit more
---

diff --git a/experiments7/doAlu16.py b/experiments7/doAlu16.py
index be28596..9fdf10b 100755
--- a/experiments7/doAlu16.py
+++ b/experiments7/doAlu16.py
@@ -163,7 +163,7 @@ class ALU16(Module):
             ])) + v_margin
 
             # experiment, over-ride
-            width = 520
+            width = 490
             #width = 1310
             #height = 370
 
@@ -251,14 +251,14 @@ def scriptMain(editor=None, **kwargs):
     alu16 = ALU16(
         'alu16', editor, submodules=[add, sub],
         north_pins=[
-            {'net': 'o({})', 'x': 255.0+o, 'delta': -5.0, 'repeat': BIT_WIDTH},
+            {'net': 'o({})', 'x': 245.0+o, 'delta': 5.0, 'repeat': BIT_WIDTH},
             {'net': 'op'},
         ],
         south_pins=[
-            {'net': 'a({})', 'x': 205.0+o, 'delta': 10.0, 'repeat': BIT_WIDTH},
-            {'net': 'b({})', 'x': 210.0+o, 'delta': 10.0, 'repeat': BIT_WIDTH},
+            {'net': 'a({})', 'x': 195.0+o, 'delta': 10.0, 'repeat': BIT_WIDTH},
+            {'net': 'b({})', 'x': 200.0+o, 'delta': 10.0, 'repeat': BIT_WIDTH},
         ],
-        west_pins=[
+        east_pins=[
             {'net': 'rst', 'y': 10.0, 'layer': 'METAL2'},
         ],
     )