From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 27 Sep 2020 21:23:02 +0000 (+0000)
Subject: add soc ioring
X-Git-Tag: partial-core-ls180-gdsii~72
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=889e8a4787269a8f171232346f2a065a05c9f7f3;p=soclayout.git

add soc ioring
---

diff --git a/experiments9/coriolis2/ioring.py b/experiments9/coriolis2/ioring.py
new file mode 100644
index 0000000..6d28498
--- /dev/null
+++ b/experiments9/coriolis2/ioring.py
@@ -0,0 +1,150 @@
+#!/usr/bin/env python
+
+from helpers import l, u, n
+from pinparse import Parse
+import os
+
+pth = os.path.abspath(__file__)
+pth = os.path.split(pth)[0]
+p = Parse("%s/ls180" % pth, verify=False)
+print dir(p)
+
+print p.muxed_cells
+print p.muxed_cells_bank
+
+ps = [''] * 32
+pn = [''] * 32
+pe = [''] * 32
+pw = [''] * 32
+pads = {'N': pn, 'S': ps, 'E': pe, 'W': pw}
+
+iopads = []
+
+for (padnum, name, _), bank in zip(p.muxed_cells, p.muxed_cells_bank):
+    padnum = int(padnum)
+    start = p.bankstart[bank]
+    banknum = padnum - start
+    print banknum, name, bank
+    padbank = pads[bank]
+    # VSS
+    if name.startswith('vss'):
+        #name = 'p_vssick_' + name[-1]
+        #name = 'p_vsseck_0'
+        #name = 'vss'
+        name = ''
+    # VDD
+    elif name.startswith('vdd'):
+        #name = 'p_vddick_' + name[-1]
+        #name = 'p_vddeck_0'
+        #name = 'vdd'
+        name = ''
+    # SYS
+    elif name.startswith('sys'):
+        if name == 'sys_clk':
+            name = 'p_sys_clk_0'
+        elif name == 'sys_rst':
+            #name = 'p_sys_rst_1'
+            pass
+        else:
+            name = ''
+    # SPI Card
+    elif name.startswith('mspi0') or name.startswith('mspi1'):
+        suffix = name[6:]
+        if suffix == 'ck':
+            suffix = 'clk'
+        elif suffix == 'nss':
+            suffix = 'cs_n'
+        if name.startswith('mspi1'):
+            prefix = 'spi_master_'
+        else:
+            prefix = 'spisdcard_'
+        name = prefix + suffix
+    # SD/MMC
+    elif name.startswith('sd0'):
+        if name.startswith('sd0_d'):
+            i = name[5:]
+            name = 'sdcard_data' + i
+            name2 = 'sdcard_data_%%s(%s)' % i
+            pad = [name, name, name2 % 'o', name2 % 'i', 'sdcard_data_oe']
+            iopads.append(pad)
+        elif name.startswith('sd0_cmd'):
+            name = 'sdcard_cmd'
+            name2 = 'sdcard_cmd_%s'
+            pad = [name, name, name2 % 'o', name2 % 'i', name2 % 'oe']
+            iopads.append(pad)
+        else:
+            name = 'sdcard_' + name[4:]
+    # SDRAM
+    elif name.startswith('sdr'):
+        if name == 'sdr_clk':
+            name = 'sdram_clock'
+        elif name.startswith('sdr_ad'):
+            name = 'sdram_a_' + name[6:]
+        elif name.startswith('sdr_ba'):
+            name = 'sdram_ba_' + name[-1]
+        elif name.startswith('sdr_dqm'):
+            name = 'sdram_dm_' + name[-1]
+            if name[-1] == '1': # XXX skip sdram_dm_1 for now
+                name = ''
+        elif name.startswith('sdr_d'):
+            i = name[5:]
+            name = 'sdram_dq_' + i
+            name2 = 'sdram_dq_%%s(%s)' % i
+            pad = [name, name, name2 % 'o', name2 % 'i', 'sdram_dq_oe']
+            iopads.append(pad)
+        elif name == 'sdr_csn0':
+            name = 'sdram_cs_n'
+        elif name[-1] == 'n':
+            name = 'sdram_' + name[4:-1] + '_n'
+        else:
+            name = 'sdram_' + name[4:]
+    # UART
+    elif name.startswith('uart'):
+        name = 'uart_' + name[6:]
+    # GPIO
+    elif name.startswith('gpio'):
+        i = name[7:]
+        name = 'gpio_' + i
+        name2 = 'gpio_%%s(%s)' % i
+        pad = [name, name, name2 % 'o', name2 % 'i', name2 % 'oe']
+        print ("GPIO pad", name, pad)
+        iopads.append(pad)
+    # PWM
+    elif name.startswith('pwm'):
+        name = name[:-4]
+    padbank[banknum] = name
+
+# couple of unknown signals
+#pw[25] = 'p_sys_rst_1'
+pn[0] = 'p_vddeck_0'
+pn[1] = 'p_vsseck_0'
+ps[11] = 'p_vddick_0'
+ps[12] = 'p_vssick_0'
+
+pw = filter(lambda x:x, pw)
+ps = filter(lambda x:x, ps)
+pn = filter(lambda x:x, pn)
+pe = filter(lambda x:x, pe)
+
+print p.bankstart
+print pn
+print ps
+print pe
+print pw
+
+# missing (TODO)
+#pw[11] = 'i2c_scl'
+#pw[12] = 'i2c_sda'
+
+
+chip = { 'pads.ioPadGauge' : 'pxlib',
+         'pads.south'      : ps,
+          'pads.east'       : pe,
+          'pads.north'      : pn,
+          'pads.west'       : pw,
+            #[ 'f_3', 'f_2'       , 'p_clk_0', 'f_1'       , 'f_0'     ]
+          'core.size'       : ( l(13000), l(13000) ),
+          'chip.size'       : ( l(17000), l(17000) ),
+          'chip.clockTree'  : True,
+          'pads.instances' : iopads
+       }
diff --git a/pinmux b/pinmux
new file mode 160000
index 0000000..99e08da
--- /dev/null
+++ b/pinmux
@@ -0,0 +1 @@
+Subproject commit 99e08dab7b0306525b8b3fb0783c623df8d9f8c5