From: Richard Sandiford Date: Wed, 14 Aug 2019 09:22:23 +0000 (+0000) Subject: [AArch64] Use SVE MOV /M of scalars X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=88a37c4d72899c5a3f5a7b2bca0ae0096f3270a3;p=gcc.git [AArch64] Use SVE MOV /M of scalars This patch uses MOV /M to optimise selects between a duplicated scalar variable and a vector. 2019-08-14 Richard Sandiford Kugan Vivekanandarajah gcc/ * config/aarch64/aarch64-sve.md (*aarch64_sel_dup): New pattern. gcc/testsuite/ * g++.target/aarch64/sve/dup_sel_1.C: New test. * g++.target/aarch64/sve/dup_sel_2.C: Likewise. * g++.target/aarch64/sve/dup_sel_3.C: Likewise. * g++.target/aarch64/sve/dup_sel_4.C: Likewise. * g++.target/aarch64/sve/dup_sel_5.C: Likewise. * g++.target/aarch64/sve/dup_sel_6.C: Likewise. Co-Authored-By: Kugan Vivekanandarajah From-SVN: r274442 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 777f1c87874..73156f105c3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2019-08-14 Richard Sandiford + Kugan Vivekanandarajah + + * config/aarch64/aarch64-sve.md (*aarch64_sel_dup): New pattern. + 2019-08-14 Richard Sandiford Kugan Vivekanandarajah diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 1bdfc4706d1..e12b5d954f8 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -3070,6 +3070,29 @@ [(set_attr "movprfx" "*,*,*,*,yes,yes,yes")] ) +;; Optimize selects between a duplicated scalar variable and another vector, +;; the latter of which can be a zero constant or a variable. Treat duplicates +;; of GPRs as being more expensive than duplicates of FPRs, since they +;; involve a cross-file move. +(define_insn "*aarch64_sel_dup" + [(set (match_operand:SVE_ALL 0 "register_operand" "=?w, w, ??w, ?&w, ??&w, ?&w") + (unspec:SVE_ALL + [(match_operand: 3 "register_operand" "Upa, Upa, Upl, Upl, Upl, Upl") + (vec_duplicate:SVE_ALL + (match_operand: 1 "register_operand" "r, w, r, w, r, w")) + (match_operand:SVE_ALL 2 "aarch64_simd_reg_or_zero" "0, 0, Dz, Dz, w, w")] + UNSPEC_SEL))] + "TARGET_SVE" + "@ + mov\t%0., %3/m, %1 + mov\t%0., %3/m, %1 + movprfx\t%0., %3/z, %0.\;mov\t%0., %3/m, %1 + movprfx\t%0., %3/z, %0.\;mov\t%0., %3/m, %1 + movprfx\t%0, %2\;mov\t%0., %3/m, %1 + movprfx\t%0, %2\;mov\t%0., %3/m, %1" + [(set_attr "movprfx" "*,*,yes,yes,yes,yes")] +) + ;; ------------------------------------------------------------------------- ;; ---- [INT,FP] Compare and select ;; ------------------------------------------------------------------------- diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a2507f729c0..de09124e7e0 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,13 @@ +2019-08-14 Richard Sandiford + Kugan Vivekanandarajah + + * g++.target/aarch64/sve/dup_sel_1.C: New test. + * g++.target/aarch64/sve/dup_sel_2.C: Likewise. + * g++.target/aarch64/sve/dup_sel_3.C: Likewise. + * g++.target/aarch64/sve/dup_sel_4.C: Likewise. + * g++.target/aarch64/sve/dup_sel_5.C: Likewise. + * g++.target/aarch64/sve/dup_sel_6.C: Likewise. + 2019-08-14 Richard Sandiford Kugan Vivekanandarajah diff --git a/gcc/testsuite/g++.target/aarch64/sve/dup_sel_1.C b/gcc/testsuite/g++.target/aarch64/sve/dup_sel_1.C new file mode 100644 index 00000000000..a59862cf9c3 --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/sve/dup_sel_1.C @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=256" } */ + +#include + +typedef int32_t vnx4si __attribute__((vector_size(32))); + +void +foo (int32_t val) +{ + register vnx4si x asm ("z0"); + register vnx4si y asm ("z0"); + asm volatile ("" : "=w" (y)); + val += 1; + vnx4si z = { val, val, val, val, val, val, val, val }; + x = (vnx4si) { -1, 0, 0, -1, 0, -1, 0, -1 } ? z : y; + asm volatile ("" :: "w" (x)); +} + +/* { dg-final { scan-assembler {\tmov\tz0\.s, p[0-7]/m, w[0-9]+\n} } } */ +/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */ diff --git a/gcc/testsuite/g++.target/aarch64/sve/dup_sel_2.C b/gcc/testsuite/g++.target/aarch64/sve/dup_sel_2.C new file mode 100644 index 00000000000..47aad2d580f --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/sve/dup_sel_2.C @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=256" } */ + +#include + +typedef int32_t vnx4si __attribute__((vector_size(32))); + +void +foo (int32_t val) +{ + register vnx4si x asm ("z0"); + register vnx4si y asm ("z1"); + asm volatile ("" : "=w" (y)); + val += 1; + vnx4si z = { val, val, val, val, val, val, val, val }; + x = (vnx4si) { -1, 0, 0, -1, 0, -1, 0, -1 } ? z : y; + asm volatile ("" :: "w" (x)); +} + +/* { dg-final { scan-assembler {\tmovprfx\tz0, z1\n\tmov\tz0\.s, p[0-7]/m, w[0-9]+\n} } } */ diff --git a/gcc/testsuite/g++.target/aarch64/sve/dup_sel_3.C b/gcc/testsuite/g++.target/aarch64/sve/dup_sel_3.C new file mode 100644 index 00000000000..e8ec6f8b4b3 --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/sve/dup_sel_3.C @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=256" } */ + +#include + +typedef int32_t vnx4si __attribute__((vector_size(32))); +typedef float vnx4sf __attribute__((vector_size(32))); + +void +foo (float val) +{ + register vnx4sf x asm ("z0"); + register vnx4sf y asm ("z0"); + asm volatile ("" : "=w" (y)); + vnx4sf z = { val, val, val, val, val, val, val, val }; + x = (vnx4si) { -1, 0, 0, -1, 0, -1, 0, -1 } ? z : y; + asm volatile ("" :: "w" (x)); +} + +/* { dg-final { scan-assembler {\tmov\tz0\.s, p[0-7]/m, s[0-9]+\n} } } */ +/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */ diff --git a/gcc/testsuite/g++.target/aarch64/sve/dup_sel_4.C b/gcc/testsuite/g++.target/aarch64/sve/dup_sel_4.C new file mode 100644 index 00000000000..32ca594398e --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/sve/dup_sel_4.C @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=256" } */ + +#include + +typedef int32_t vnx4si __attribute__((vector_size(32))); +typedef float vnx4sf __attribute__((vector_size(32))); + +void +foo (float val) +{ + register vnx4sf x asm ("z0"); + register vnx4sf y asm ("z1"); + asm volatile ("" : "=w" (y)); + vnx4sf z = { val, val, val, val, val, val, val, val }; + x = (vnx4si) { -1, 0, 0, -1, 0, -1, 0, -1 } ? z : y; + asm volatile ("" :: "w" (x)); +} + +/* { dg-final { scan-assembler {\tmovprfx\tz0, z1\n\tmov\tz0\.s, p[0-7]/m, s[0-9]+\n} } } */ diff --git a/gcc/testsuite/g++.target/aarch64/sve/dup_sel_5.C b/gcc/testsuite/g++.target/aarch64/sve/dup_sel_5.C new file mode 100644 index 00000000000..2fb903a9151 --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/sve/dup_sel_5.C @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=256" } */ + +#include + +typedef int32_t vnx4si __attribute__((vector_size(32))); + +void +foo (int32_t val) +{ + register vnx4si x asm ("z0"); + val += 1; + vnx4si y = { val, val, val, val, val, val, val, val }; + x = (vnx4si) { -1, 0, 0, -1, 0, -1, 0, -1 } ? y : (vnx4si) { 0 }; + asm volatile ("" :: "w" (x)); +} + +/* { dg-final { scan-assembler {\tmovprfx\tz0\.s, p[0-7]/z, z0\.s\n\tmov\tz0\.s, p[0-7]/m, w[0-9]+\n} } } */ diff --git a/gcc/testsuite/g++.target/aarch64/sve/dup_sel_6.C b/gcc/testsuite/g++.target/aarch64/sve/dup_sel_6.C new file mode 100644 index 00000000000..f2b0181bb82 --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/sve/dup_sel_6.C @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=256" } */ + +#include + +typedef int32_t vnx4si __attribute__((vector_size(32))); +typedef float vnx4sf __attribute__((vector_size(32))); + +void +foo (float val) +{ + register vnx4sf x asm ("z0"); + vnx4sf y = { val, val, val, val, val, val, val, val }; + x = (vnx4si) { -1, 0, 0, -1, 0, -1, 0, -1 } ? y : (vnx4sf) { 0 }; + asm volatile ("" :: "w" (x)); +} + +/* { dg-final { scan-assembler {\tmovprfx\tz0\.s, p[0-7]/z, z0\.s\n\tmov\tz0\.s, p[0-7]/m, s[0-9]+\n} } } */