From: lkcl <lkcl@web>
Date: Wed, 8 Sep 2021 13:35:04 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~179
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=88a823723277b6f79040042f9f2c1a00b33d7f8d;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index ecd2c495e..2aae637d5 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -19,6 +19,12 @@ be a "co-result". Thus, if the arithmetic result is Vectorised, so
 is the CR Field "co-result", which puts both firmly out of scope for
 this section.
 
+Examples of v3.0B instructions to which this section does
+apply is `mfcr` (3 bit operands) and `crnor` (5 bit operands).
+Examples to which this section does **not** apply include
+`fadds.` and `subf.` which both produce arithmetic results
+(and a CR Field co-result).
+
 Other modes are still applicable and include:
 
 * **Data-dependent fail-first**.