From: lkcl <lkcl@web>
Date: Thu, 15 Sep 2022 11:35:28 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~429
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=88ad8377e3972f8455521d4773d78f222de5adf5;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 9419a6d9f..fdb1adff5 100644
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -349,7 +349,8 @@ provided in the Scalar Power ISA without one single explicit FP16 or BF16
 all 64-bit encodings.
 
 As SVP64Single is new and still under development, space for it may
-instead be `RESERVED`. It is however necessary as there are limitations
+instead be `RESERVED`. It is however necessary in *some* form
+as there are limitations
 in SVP64 Register numbering, particularly for 4-operand instructions,
 that can only be easily overcome by SVP64Single.
 
@@ -535,9 +536,9 @@ is based loosely around Public v3.1 EXT001 Encoding.[^ext001]
 | 0-5 | 6 | 7 | 8-31  | Description               |
 |-----|---|---|-------|---------------------------|
 | PO  | 0 | 0 | 0000  | new-suffix `RESERVED1`               |
-| PO  | 0 | 0 | !zero | new-suffix, scalar (SVP64Single) |
+| PO  | 0 | 0 | !zero | new-suffix, scalar (SVP64Single), or `RESERVED3` |
 | PO  | 1 | 0 | 0000  | new scalar-only word, or `RESERVED2`               |
-| PO  | 1 | 0 | !zero | old-suffix, scalar (SVP64Single) |
+| PO  | 1 | 0 | !zero | old-suffix, scalar (SVP64Single), or `RESERVED4` |
 | PO  | 0 | 1 | nnnn  | new-suffix, vector (SVP64)       |
 | PO  | 1 | 1 | nnnn  | old-suffix, vector (SVP64)       |
 
@@ -560,6 +561,9 @@ is based loosely around Public v3.1 EXT001 Encoding.[^ext001]
   except that it is equivalent to hard-coded VL=1
   at all times. Predication is permitted, Element-width-overrides is
   permitted, Saturation is permitted.
+  If not allocated within the scope of this RFC
+  then these are requested to be `RESERVED` for a future Simple-V
+  proposal.
 * **SVP64** - a (well-defined, 2 years) DRAFT Proposal for a Vectorisation
   Augmentation of suffixes.
 
@@ -569,8 +573,8 @@ allocation to new POs, `RESERVED2` does not.[^only2]
 
 |          | Scalar (bit7=0,8-31=0000) | Scalar (bit7=0,8-31=!zero)| Vector (bit7=1)  |
 |----------|---------------------------|---------------------------|------------------|
-|new bit6=0| `RESERVED1`:{EXT200-263}  | SVP64-Single:{EXT200-263} | SVP64:{EXT200-263} |
-|old bit6=1| `RESERVED2`:{EXT300-363}  | SVP64-Single:{EXT000-063}   | SVP64:{EXT000-063}   |
+|new bit6=0| `RESERVED1`:{EXT200-263}  | `RESERVED3`:SVP64-Single:{EXT200-263} | SVP64:{EXT200-263} |
+|old bit6=1| `RESERVED2`:{EXT300-363}  | `RESERVED4`:SVP64-Single:{EXT000-063}   | SVP64:{EXT000-063}   |
 
 * **`RESERVED2`:{EXT300-363}** (not strictly necessary to be added) is not
   and **cannot** ever be Vectorised or Augmented by Simple-V or any future
@@ -582,13 +586,13 @@ allocation to new POs, `RESERVED2` does not.[^only2]
   *but the option to do so exists* should an Implementor choose to do so.
   This is unlike `EXT300-363` which may **never** be Simple-V-Augmented
   under any circumstances.
-* **`SVP64-Single:{EXT200-263}`** - Major opcodes 200-263 with
+* **RESERVED3:`SVP64-Single:{EXT200-263}`** - Major opcodes 200-263 with
   Single-Augmentation, providing a one-bit predicate mask, element-width
   overrides on source and destination, and the option to extend the Scalar
   Register numbering (r0-32 extends to r0-127).  **Placing of alternative
   instruction encodings other than those exactly defined in EXT200-263
   is prohibited**.
-* **`SVP64-Single:{EXT000-063}`** - Major opcodes 000-063 with
+* **RESERVED4:`SVP64-Single:{EXT000-063}`** - Major opcodes 000-063 with
   Single-Augmentation, just like SVP64-Single on EXT200-263, these are
   in effect Single-Augmented-Prefixed variants of the v3.0 32-bit Power ISA.
   Alternative instruction encodings other than the exact same 32-bit word
@@ -698,6 +702,14 @@ Vectorisation of EXT001 is prohibited.
 |--------|---|---|-------|--------|---------|
 | PO (9)?| 1 | 1 | nnnn  | PO2    | SVP64:{EXT000-063} |
 
+# Example Legal Encodings and RESERVED spaces
+
+This section illustrates what is legal encoding, what is not, and
+why the 4 spaces should be `RESERVED` even if not allocated as part
+of this RFC.
+
+
+
 \newpage{}
 # Use cases