From: whitequark <cz@m-labs.hk>
Date: Sat, 22 Dec 2018 00:53:40 +0000 (+0000)
Subject: back.verilog: do not rename internal signals.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=88afdcfc70b0e33ed9943155e20e96719aabccf6;p=nmigen.git

back.verilog: do not rename internal signals.

_0_ is not really any better than \$13, and the latter at least has
continuity between nMigen, RTLIL and Verilog.
---

diff --git a/nmigen/back/verilog.py b/nmigen/back/verilog.py
index 5c8e08d..249075d 100644
--- a/nmigen/back/verilog.py
+++ b/nmigen/back/verilog.py
@@ -28,7 +28,7 @@ proc_arst
 proc_dff
 proc_clean
 memory_collect
-write_verilog
+write_verilog -norename
 # Make sure there are no undriven wires in generated RTLIL.
 proc
 select -assert-none w:* i:* %a %d o:* %a %ci* %d c:* %co* %a %d n:$* %d