From: lkcl <lkcl@web>
Date: Thu, 16 Jun 2022 11:14:33 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1759
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=88b02a8ed1a9df210a4b0859213f3394206df6a7;p=libreriscv.git

---

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index 0ec81e92b..57272d3eb 100644
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -2,28 +2,27 @@
 
 # SV Vector Operations.
 
-* TODO merge old standards page [[simple_v_extension/vector_ops/]]
-* bugreport <https://bugs.libre-soc.org/show_bug.cgi?id=142>
-
-The core OpenPOWER ISA was designed as scalar: SV provides a level of abstraction to add variable-length element-independent parallelism. However, certain classes of instructions only make sense in a Vector context: AVX512 conflictd for example.  This section includes such examples.  Many of them are from the RISC-V Vector ISA (with thanks to the efforts of RVV's contributors)
-
-Notes:
-
-* Some of these actually could be added to a scalar ISA as bitmanipulation instructions.  These are separated out into their own section.
-* Instructions suited to 3D GPU workloads (dotproduct, crossproduct, normalise) are out of scope: this document is for more general-purpose instructions that underpin and are critical to general-purpose Vector workloads (including GPU and VPU)
-* Instructions related to the adaptation of CRs for use as predicate masks are covered separately, by crweird operations.  See [[sv/cr_int_predication]].
-
 Links:
 
+* TODO merge old standards page [[simple_v_extension/vector_ops/]]
 * <https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-register-gather-instructions>
 * <http://0x80.pl/notesen/2016-10-23-avx512-conflict-detection.html> conflictd example
 * <https://lists.libre-soc.org/pipermail/libre-soc-dev/2022-May/004884.html>
 * <https://bugs.libre-soc.org/show_bug.cgi?id=213>
 * <https://bugs.libre-soc.org/show_bug.cgi?id=142> specialist vector ops
- out of scope for this document
+ out of scope for this document [[openpower/sv/3d_vector_ops]]
 * [[simple_v_extension/specification/bitmanip]] previous version,
   contains pseudocode for sof, sif, sbf
 
+
+The core OpenPOWER ISA was designed as scalar: SV provides a level of abstraction to add variable-length element-independent parallelism. However, certain classes of instructions only make sense in a Vector context: AVX512 conflictd for example.  This section includes such examples.  Many of them are from the RISC-V Vector ISA (with thanks to the efforts of RVV's contributors)
+
+Notes:
+
+* Some of these actually could be added to a scalar ISA as bitmanipulation instructions.  These are separated out into their own section.
+* Instructions suited to 3D GPU workloads (dotproduct, crossproduct, normalise) are out of scope: this document is for more general-purpose instructions that underpin and are critical to general-purpose Vector workloads (including GPU and VPU)
+* Instructions related to the adaptation of CRs for use as predicate masks are covered separately, by crweird operations.  See [[sv/cr_int_predication]].
+
 # Vector
 
 Both of these instructions may be synthesised from SVP64 Vector