From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Thu, 17 Oct 2013 15:20:45 +0000 (-0500)
Subject: dev: Allow additional UART interrupts to be set
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=88b811b4efdb4c4defd4fa5a2426a5012939b39c;p=gem5.git

dev: Allow additional UART interrupts to be set

This patch allows setting a few additional interrupts for status
changes that should never occur.
---

diff --git a/src/dev/arm/pl011.cc b/src/dev/arm/pl011.cc
index 2b4225ad5..b47d0e9fb 100644
--- a/src/dev/arm/pl011.cc
+++ b/src/dev/arm/pl011.cc
@@ -211,10 +211,14 @@ Pl011::write(PacketPtr pkt)
       case UART_IMSC:
         imsc = data;
 
-        if (imsc.rimim || imsc.ctsmim || imsc.dcdmim || imsc.dsrmim
-             || imsc.feim || imsc.peim || imsc.beim || imsc.oeim || imsc.rsvd)
+        if (imsc.feim || imsc.peim || imsc.beim || imsc.oeim || imsc.rsvd)
             panic("Unknown interrupt enabled\n");
 
+        // rimim, ctsmim, dcdmim, dsrmim can be enabled but are ignored
+        // they are supposed to interrupt on a change of status in the line
+        // which we should never have since our terminal is happy to always
+        // receive bytes.
+
         if (imsc.txim) {
             DPRINTF(Uart, "Writing to IMSC: TX int enabled, scheduling interruptt\n");
             rawInt.txim = 1;