From: Michael Betz Date: Tue, 23 Apr 2019 07:22:48 +0000 (+0200) Subject: build/xilinx/ise.py: write .v file for post synthesis sim X-Git-Tag: 24jan2021_ls180~1295 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=88b882c7e080bb13863e9ff490b81c36180051a6;p=litex.git build/xilinx/ise.py: write .v file for post synthesis sim --- diff --git a/litex/build/xilinx/ise.py b/litex/build/xilinx/ise.py index cd3e2d18..0bb19d49 100644 --- a/litex/build/xilinx/ise.py +++ b/litex/build/xilinx/ise.py @@ -108,6 +108,11 @@ def _run_ise(build_name, ise_path, source, mode, ngdbuild_opt, ext = "ngc" build_script_contents += """ xst -ifn {build_name}.xst{fail_stmt} +""" + + # This generates a .v file for post synthesis simulation + build_script_contents += """ +netgen -ofmt verilog -w -sim {build_name}.{ext} {build_name}_synth.v """ build_script_contents += """