From: lkcl <lkcl@web>
Date: Mon, 2 Aug 2021 12:00:45 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~532
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=88c3104bab03eed91a852c70ba4fdef170632f79;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index bbc445fa6..d0ca40921 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -113,7 +113,7 @@ by the bit from the Branch `BI` field.
 
 Available options to combine:
 
-* `BO` to select whether the CR bit being tested is zero or nonzero
+* `BO[1]` to select whether the CR bit being tested is zero or nonzero
 * `R30` and `~R30` and other predicate mask options including CR and
   inverted CR bit testing
 * `sz` and `SNZ` to insert either zeros or ones in place of masked-out