From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 2 Aug 2014 19:54:02 +0000 (+0200)
Subject: Be more conservative with printing decimal numbers in verilog backend
X-Git-Tag: yosys-0.4~320
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=88cf00ce7874ec7951b09d85e959dd2c6ed261b6;p=yosys.git

Be more conservative with printing decimal numbers in verilog backend
---

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index c691eae60..605616b31 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -163,11 +163,12 @@ void dump_const(FILE *f, const RTLIL::Const &data, int width = -1, int offset =
 				log_assert(i < (int)data.bits.size());
 				if (data.bits[i] != RTLIL::S0 && data.bits[i] != RTLIL::S1)
 					goto dump_bits;
+				if (data.bits[i] == RTLIL::S1 && (i - offset) == 31)
+					goto dump_bits;
 				if (data.bits[i] == RTLIL::S1)
 					val |= 1 << (i - offset);
 			}
-			// fprintf(f, "%s32'sd%u", val < 0 ? "-" : "", abs(val));
-			fprintf(f, "%d", val);
+			fprintf(f, "32'%sd%d", set_signed ? "s" : "", val);
 		} else {
 	dump_bits:
 			fprintf(f, "%d'%sb", width, set_signed ? "s" : "");