From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Apr 2019 23:29:14 +0000 (-0700)
Subject: Use -map instead of -symbols for aiger
X-Git-Tag: working-ls180~1237^2~236
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=88d43a519bd0ea9657baba8bf9bc6a845b6cf14d;p=yosys.git

Use -map instead of -symbols for aiger
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index ec4a28d08..17d082833 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -407,7 +407,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 
 	handle_loops(design);
 
-	Pass::call(design, stringf("write_xaiger -O -symbols %s/input.aig; ", tempdir_name.c_str()));
+	Pass::call(design, stringf("write_xaiger -O -map %s/input.sym %s/input.aig; ", tempdir_name.c_str(), tempdir_name.c_str()));
 
 	design->selection_stack.pop_back();
 
@@ -523,7 +523,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 		bool builtin_lib = liberty_file.empty();
 		RTLIL::Design *mapped_design = new RTLIL::Design;
 		//parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode);
-		AigerReader reader(mapped_design, ifs, "\\netlist", "" /* clk_name */, "" /* map_filename */, true /* wideports */);
+		buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym");
+		AigerReader reader(mapped_design, ifs, "\\netlist", "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
 		reader.parse_xaiger();
 
 		ifs.close();