From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 10 May 2019 05:02:50 +0000 (+0100)
Subject: update cam test
X-Git-Tag: div_pipeline~2084
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=88d73707aa1b54835398a7a17f2699a802ae6076;p=soc.git

update cam test
---

diff --git a/src/TLB/Cam.py b/src/TLB/Cam.py
index 3c499211..46ba27bd 100644
--- a/src/TLB/Cam.py
+++ b/src/TLB/Cam.py
@@ -2,8 +2,9 @@ from nmigen import Array, Cat, Module, Signal
 from nmigen.lib.coding import Decoder
 from nmigen.cli import main #, verilog
 
-from CamEntry import CamEntry
-from AddressEncoder import AddressEncoder
+from .CamEntry import CamEntry
+from .AddressEncoder import AddressEncoder
+
 
 class Cam():
     """ Content Addressable Memory (CAM)
diff --git a/src/TLB/test/test_cam.py b/src/TLB/test/test_cam.py
index 0047f538..f11c48ad 100644
--- a/src/TLB/test/test_cam.py
+++ b/src/TLB/test/test_cam.py
@@ -1,12 +1,8 @@
-import sys
-sys.path.append("../src")
-sys.path.append("../../TestUtil")
-
 from nmigen.compat.sim import run_simulation
 
-from Cam import Cam
+from TLB.Cam import Cam
 
-from test_helper import assert_eq, assert_ne, assert_op
+from TestUtil.test_helper import assert_eq, assert_ne, assert_op
 
 # This function allows for the easy setting of values to the Cam
 # Arguments:
@@ -63,7 +59,7 @@ def check_all(dut, mm, sm, ma, mm_op, sm_op, ma_op):
     yield from check_single_match(dut, sm, sm_op)
     yield from check_match_address(dut, ma, ma_op)
 
-def testbench(dut):
+def tbench(dut):
     # NA
     enable = 0
     write_enable = 0
@@ -201,7 +197,10 @@ def testbench(dut):
     yield
 
 
-if __name__ == "__main__":
+def test_cam():
     dut = Cam(4, 4)
-    run_simulation(dut, testbench(dut), vcd_name="Waveforms/test_cam.vcd")
+    run_simulation(dut, tbench(dut), vcd_name="Waveforms/test_cam.vcd")
     print("Cam Unit Test Success")
+
+if __name__ == "__main__":
+    test_cam()