From: Mehul <Mehul@web>
Date: Sun, 22 Aug 2021 10:15:11 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~333
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=88ebfa70a765534c4633ade780576c3e8371fbf2;p=libreriscv.git

---

diff --git a/about_us.mdwn b/about_us.mdwn
index 5714112c0..72bfde53e 100644
--- a/about_us.mdwn
+++ b/about_us.mdwn
@@ -186,6 +186,12 @@ TODO, Adithya
 * Programming Languages: Python, Verilog, Ng-spice
 * Availability: 4-6 hours per week
 
+### [[oa/Mehul N]]
+
+* Interests: Digital Design, Verification, IC Fabrication
+* Programming Languages: Verilog, System Verilog, UVM
+* Availability: ~ 6-8 hours/week
+* Experience: SoC Verification Intern, Research Intern at KIST
 
 ### [[oa/sparsha]]