From: lkcl <lkcl@web>
Date: Mon, 16 Aug 2021 15:32:17 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~425
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=89050aa2c862dd1c476dd5794b61794c38f5419b;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 7d3aec698..5bf1f0fc3 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -33,7 +33,8 @@ test-and-branch, if a predicate mask is all zeros a large batch of
 instructions may be masked out to `nop`, and it would waste
 CPU cycles not only to run them but also to load the predicate
 mask repeatedly for each one.  3D GPU ISAs can test for this scenario
-and jump over the masked-out operations.
+and jump over the fully-masked-out operations, by spotting that
+all Conditions are zero.
 Therefore, in order to be commercially competitive, `sv.bc` and
 other Vector-aware Branch Conditional instructions are a high priority
 for 3D GPU workloads.