From: Tobias Platen <tplaten@posteo.de>
Date: Mon, 20 Apr 2020 14:50:42 +0000 (+0200)
Subject: add with carry cleanup and test case
X-Git-Tag: div_pipeline~1420
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8910ecb7f1e90fb41fe7ae705f1dfb9f4c534be7;p=soc.git

add with carry cleanup and test case
---

diff --git a/src/soc/simulator/internalop_sim.py b/src/soc/simulator/internalop_sim.py
index 726124a3..b54b29b0 100644
--- a/src/soc/simulator/internalop_sim.py
+++ b/src/soc/simulator/internalop_sim.py
@@ -59,7 +59,7 @@ class RegFile:
         self.sprs = {}
 
     def write_reg(self, regnum, value):
-        all1s = (1<<64)-1 # 64 bits worth of 1s
+        all1s = (1 << 64)-1  # 64 bits worth of 1s
         value &= all1s
         print("Writing {:x} to reg r{}".format(value, regnum))
         self.regfile[regnum] = value
@@ -106,7 +106,7 @@ class InternalOpSimulator:
             assert False, "Not implemented"
 
     def alu_op(self, pdecode2):
-        all1s = (1<<64)-1 # 64 bits worth of 1s
+        all1s = (1 << 64)-1  # 64 bits worth of 1s
         internal_op = yield pdecode2.dec.op.internal_op
         operand1 = 0
         operand2 = 0
@@ -142,14 +142,11 @@ class InternalOpSimulator:
                                      carry=carry)
 
         cry_out = yield pdecode2.dec.op.cry_out
-        ## TODO   yield pdecode2.dec.op.rc
-        if(cry_out==1):
-            if(result > 0xFFFFFFFF):
-                self.carry_out = 1
-            else:
-                self.carry_out = 0
-            
-            
+        # TODO   yield pdecode2.dec.op.rc
+        if cry_out == 1:
+            self.carry_out = (result >> 64)
+            print("setting carry_out", self.carry_out)
+
         ro_ok = yield pdecode2.e.write_reg.ok
         if ro_ok:
             ro_sel = yield pdecode2.e.write_reg.data
diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index 068beacd..c170397e 100644
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -97,6 +97,17 @@ class DecoderTestCase(FHDLTestCase):
         with Program(lst) as program:
             self.run_tst_program(program, [1, 2, 3, 4, 5])
 
+    def test_add_with_carry(self):
+        lst = ["addi 1, 0, 5",
+               "neg 1, 1",
+               "addi 2, 0, 7",
+               "neg 2, 2",
+               "addc 3, 2, 1",
+               "addi 3, 3, 1"
+               ]
+        with Program(lst) as program:
+            self.run_tst_program(program, [1, 2, 3])
+
     def run_tst_program(self, prog, reglist):
         simulator = InternalOpSimulator()
         self.run_tst(prog, simulator)