From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 4 Jul 2020 20:01:34 +0000 (+0100)
Subject: add pspec to test_core.py
X-Git-Tag: div_pipeline~162^2~77
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=89280fab4a8ddbebd0fb5cdc5901f8dff4d68f1d;p=soc.git

add pspec to test_core.py
---

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 904aa76d..edc6c7e3 100644
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -14,7 +14,7 @@ from soc.decoder.power_decoder import create_pdecode
 from soc.decoder.power_decoder2 import PowerDecode2
 from soc.decoder.isa.all import ISA
 from soc.decoder.power_enums import Function, XER_bits
-
+from soc.config.test.test_loadstore import TestMemPspec
 
 from soc.simple.core import NonProductionCore
 from soc.experiment.compalu_multi import find_ok # hack