From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 14 Mar 2019 04:42:53 +0000 (+0000)
Subject: remove extra arg from old roundz function
X-Git-Tag: ls180-24jan2020~1667
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=892d640f8224e6a52907c6899ab6ab671f5f53af;p=ieee754fpu.git

remove extra arg from old roundz function
---

diff --git a/src/add/fmul.py b/src/add/fmul.py
index 8e3ea7d5..9ed2bf39 100644
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -127,7 +127,7 @@ class FPMUL(FPBase):
             # rounding stage
 
             with m.State("round"):
-                self.roundz(m, z, z, of.roundz)
+                #self.roundz(m, z, of.roundz)
                 m.next = "corrections"
 
             # ******
diff --git a/src/add/fpbase.py b/src/add/fpbase.py
index bd203649..db95eb13 100644
--- a/src/add/fpbase.py
+++ b/src/add/fpbase.py
@@ -558,14 +558,13 @@ class FPBase:
         with m.Else():
             m.next = next_state
 
-    def roundz(self, m, z, out_z, roundz):
+    def roundz(self, m, z, roundz):
         """ performs rounding on the output.  TODO: different kinds of rounding
         """
-        #m.d.comb += out_z.copy(z) # copies input to output first
         with m.If(roundz):
-            m.d.sync += out_z.m.eq(z.m + 1) # mantissa rounds up
+            m.d.sync += z.m.eq(z.m + 1) # mantissa rounds up
             with m.If(z.m == z.m1s): # all 1s
-                m.d.sync += out_z.e.eq(z.e + 1) # exponent rounds up
+                m.d.sync += z.e.eq(z.e + 1) # exponent rounds up
 
     def corrections(self, m, z, next_state):
         """ denormalisation and sign-bug corrections