From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Sun, 22 Oct 2023 13:14:55 +0000 (+0300)
Subject: test_syscall: check MSR; update expected PC
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=893150919038d4fc9903db127eaf6b4894bcb814;p=openpower-isa.git

test_syscall: check MSR; update expected PC
---

diff --git a/src/openpower/decoder/isa/test_syscall.py b/src/openpower/decoder/isa/test_syscall.py
index 74b33683..c36dc781 100644
--- a/src/openpower/decoder/isa/test_syscall.py
+++ b/src/openpower/decoder/isa/test_syscall.py
@@ -4,21 +4,68 @@ import unittest
 
 from nmutil.formaltest import FHDLTestCase
 
+from openpower.consts import MSRb
+from openpower.consts import PIb
+from openpower.consts import DEFAULT_MSR
+from openpower.decoder.helpers import ne
 from openpower.decoder.isa.test_runner import run_tst
 from openpower.test.runner import TestRunnerBase
 from openpower.simulator.program import Program
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.decoder.selectable_int import selectconcat as concat
 
 
 class SyscallTestCase(FHDLTestCase):
-    def run_tst_program(self, prog, initial_regs=[0] * 32):
-        initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678}
+    def run_tst_program(self, prog,
+            initial_regs=None):
+        if initial_regs is None:
+            initial_regs=([0] * 32)
+        initial_regs = list(initial_regs)
+        initial_sprs = {
+            'SRR0': 0xFFFF_FFFF_FFFF_FFFF,
+            'SRR1': 0xFFFF_FFFF_FFFF_FFFF,
+        }
         sim = run_tst(prog, initial_regs,
             initial_sprs=initial_sprs,
+            initial_msr=DEFAULT_MSR,
             use_syscall_emu=True)
         sim.gpr.dump()
-        self.assertEqual(sim.spr['SRR0'], 4)                  # PC to return to: CIA+4
-        # self.assertEqual(sim.spr['SRR1'], 0x9000000000022903) # MSR to restore after sc return
-        # self.assertEqual(sim.msr, 0x9000000000000001)          # MSR changed to this by sc/trap
+
+        MSR = SelectableInt(DEFAULT_MSR, 64)
+        SRR1 = SelectableInt(0xFFFF_FFFF_FFFF_FFFF, 64)
+
+        # sc instruction
+        # 4.3.1 System Linkage Instructions
+        # 7.5.14 System Call Interrupt
+        SRR1[33:37] = 0
+        SRR1[42:48] = 0
+        SRR1[0:33] = MSR[0:33]
+        SRR1[37:42] = MSR[37:42]
+        SRR1[48:64] = MSR[48:64]
+        SRR1[PIb.TRAP] = 1
+
+        # rfid instruction
+        MSR[51] = MSR[3] & SRR1[51] | ~MSR[3] & MSR[51]
+        MSR[3] = MSR[3] & SRR1[3]
+        if ne(MSR[29:32], SelectableInt(value=0x2, bits=3)) | ne(SRR1[29:32],
+            SelectableInt(value=0x0, bits=3)):
+            MSR[29:32] = SRR1[29:32]
+        MSR[48] = SRR1[48] | SRR1[49]
+        MSR[58] = SRR1[58] | SRR1[49]
+        MSR[59] = SRR1[59] | SRR1[49]
+        MSR[0:3] = SRR1[0:3]
+        MSR[4:29] = SRR1[4:29]
+        MSR[32] = SRR1[32]
+        MSR[37:42] = SRR1[37:42]
+        MSR[49:51] = SRR1[49:51]
+        MSR[52:58] = SRR1[52:58]
+        MSR[60:64] = SRR1[60:64]
+
+        self.assertEqual(sim.spr['SRR0'], 8)    # PC to return to: CIA+4
+        self.assertEqual(sim.spr['SRR1'], SRR1) # MSR to restore after sc return
+        self.assertEqual(sim.msr, MSR)          # MSR changed to this by sc/trap
+        print("SYSCALL SRR1", hex(int(SRR1)), hex(int(sim.spr['SRR1'])))
+        print("SYSCALL  MSR", hex(int(MSR)), hex(int(sim.msr)), hex(DEFAULT_MSR))
         return sim
 
     def test_sc_getpid(self):