From: Paul Mackerras Date: Sat, 11 Jul 2020 05:40:27 +0000 (+1000) Subject: core: Don't generate logic for log data when LOG_LENGTH = 0 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=893d2bc6a24f9d1dbae374e7aa01b2abda57d140;p=microwatt.git core: Don't generate logic for log data when LOG_LENGTH = 0 This adds "if LOG_LENGTH > 0 generate" to the places in the core where log output data is latched, so that when LOG_LENGTH = 0 we don't create the logic to collect the data which won't be stored. Signed-off-by: Paul Mackerras --- diff --git a/core.vhdl b/core.vhdl index 4a83d69..c7dd3f6 100644 --- a/core.vhdl +++ b/core.vhdl @@ -202,7 +202,8 @@ begin SIM => SIM, LINE_SIZE => 64, NUM_LINES => 64, - NUM_WAYS => 2 + NUM_WAYS => 2, + LOG_LENGTH => LOG_LENGTH ) port map( clk => clk, @@ -222,6 +223,9 @@ begin icache_stall_in <= decode1_busy; decode1_0: entity work.decode1 + generic map( + LOG_LENGTH => LOG_LENGTH + ) port map ( clk => clk, rst => rst_dec1, @@ -239,7 +243,8 @@ begin decode2_0: entity work.decode2 generic map ( - EX1_BYPASS => EX1_BYPASS + EX1_BYPASS => EX1_BYPASS, + LOG_LENGTH => LOG_LENGTH ) port map ( clk => clk, @@ -261,7 +266,8 @@ begin register_file_0: entity work.register_file generic map ( - SIM => SIM + SIM => SIM, + LOG_LENGTH => LOG_LENGTH ) port map ( clk => clk, @@ -279,7 +285,8 @@ begin cr_file_0: entity work.cr_file generic map ( - SIM => SIM + SIM => SIM, + LOG_LENGTH => LOG_LENGTH ) port map ( clk => clk, @@ -292,7 +299,8 @@ begin execute1_0: entity work.execute1 generic map ( - EX1_BYPASS => EX1_BYPASS + EX1_BYPASS => EX1_BYPASS, + LOG_LENGTH => LOG_LENGTH ) port map ( clk => clk, @@ -315,6 +323,9 @@ begin ); loadstore1_0: entity work.loadstore1 + generic map ( + LOG_LENGTH => LOG_LENGTH + ) port map ( clk => clk, rst => rst_ls1, @@ -344,7 +355,8 @@ begin generic map( LINE_SIZE => 64, NUM_LINES => 64, - NUM_WAYS => 2 + NUM_WAYS => 2, + LOG_LENGTH => LOG_LENGTH ) port map ( clk => clk, diff --git a/cr_file.vhdl b/cr_file.vhdl index 37fa76b..3e65663 100644 --- a/cr_file.vhdl +++ b/cr_file.vhdl @@ -7,7 +7,9 @@ use work.common.all; entity cr_file is generic ( - SIM : boolean := false + SIM : boolean := false; + -- Non-zero to enable log data collection + LOG_LENGTH : natural := 0 ); port( clk : in std_logic; @@ -29,7 +31,6 @@ architecture behaviour of cr_file is signal crs_updated : std_ulogic_vector(31 downto 0); signal xerc : xer_common_t := xerc_init; signal xerc_updated : xer_common_t; - signal log_data : std_ulogic_vector(12 downto 0); begin cr_create_0: process(all) variable hi, lo : integer := 0; @@ -91,14 +92,18 @@ begin end process; end generate; - cr_log: process(clk) + cf_log: if LOG_LENGTH > 0 generate + signal log_data : std_ulogic_vector(12 downto 0); begin - if rising_edge(clk) then - log_data <= w_in.write_cr_enable & - w_in.write_cr_data(31 downto 28) & - w_in.write_cr_mask; - end if; - end process; - log_out <= log_data; + cr_log: process(clk) + begin + if rising_edge(clk) then + log_data <= w_in.write_cr_enable & + w_in.write_cr_data(31 downto 28) & + w_in.write_cr_mask; + end if; + end process; + log_out <= log_data; + end generate; end architecture behaviour; diff --git a/dcache.vhdl b/dcache.vhdl index 4c1db9b..ac92305 100644 --- a/dcache.vhdl +++ b/dcache.vhdl @@ -31,7 +31,9 @@ entity dcache is -- L1 DTLB number of sets TLB_NUM_WAYS : positive := 2; -- L1 DTLB log_2(page_size) - TLB_LG_PGSZ : positive := 12 + TLB_LG_PGSZ : positive := 12; + -- Non-zero to enable log data collection + LOG_LENGTH : natural := 0 ); port ( clk : in std_ulogic; @@ -463,8 +465,6 @@ architecture rtl of dcache is ptes(j + TLB_PTE_BITS - 1 downto j) := newpte; end; - signal log_data : std_ulogic_vector(19 downto 0); - begin assert LINE_SIZE mod ROW_SIZE = 0 report "LINE_SIZE not multiple of ROW_SIZE" severity FAILURE; @@ -1460,21 +1460,25 @@ begin end if; end process; - dcache_log: process(clk) + dc_log: if LOG_LENGTH > 0 generate + signal log_data : std_ulogic_vector(19 downto 0); begin - if rising_edge(clk) then - log_data <= r1.wb.adr(5 downto 3) & - wishbone_in.stall & - wishbone_in.ack & - r1.wb.stb & r1.wb.cyc & - d_out.error & - d_out.valid & - std_ulogic_vector(to_unsigned(op_t'pos(req_op), 3)) & - stall_out & - std_ulogic_vector(to_unsigned(tlb_hit_way, 3)) & - valid_ra & - std_ulogic_vector(to_unsigned(state_t'pos(r1.state), 3)); - end if; - end process; - log_out <= log_data; + dcache_log: process(clk) + begin + if rising_edge(clk) then + log_data <= r1.wb.adr(5 downto 3) & + wishbone_in.stall & + wishbone_in.ack & + r1.wb.stb & r1.wb.cyc & + d_out.error & + d_out.valid & + std_ulogic_vector(to_unsigned(op_t'pos(req_op), 3)) & + stall_out & + std_ulogic_vector(to_unsigned(tlb_hit_way, 3)) & + valid_ra & + std_ulogic_vector(to_unsigned(state_t'pos(r1.state), 3)); + end if; + end process; + log_out <= log_data; + end generate; end; diff --git a/decode1.vhdl b/decode1.vhdl index 29b7a05..d8c2b61 100644 --- a/decode1.vhdl +++ b/decode1.vhdl @@ -7,6 +7,10 @@ use work.common.all; use work.decode_types.all; entity decode1 is + generic ( + -- Non-zero to enable log data collection + LOG_LENGTH : natural := 0 + ); port ( clk : in std_ulogic; rst : in std_ulogic; @@ -357,8 +361,6 @@ architecture behaviour of decode1 is constant nop_instr : decode_rom_t := (ALU, OP_NOP, NONE, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0'); constant fetch_fail_inst: decode_rom_t := (LDST, OP_FETCH_FAILED, NONE, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0'); - signal log_data : std_ulogic_vector(12 downto 0); - begin decode1_0: process(clk) begin @@ -524,15 +526,19 @@ begin flush_out <= f.redirect; end process; - dec1_log : process(clk) + d1_log: if LOG_LENGTH > 0 generate + signal log_data : std_ulogic_vector(12 downto 0); begin - if rising_edge(clk) then - log_data <= std_ulogic_vector(to_unsigned(insn_type_t'pos(r.decode.insn_type), 6)) & - r.nia(5 downto 2) & - std_ulogic_vector(to_unsigned(unit_t'pos(r.decode.unit), 2)) & - r.valid; - end if; - end process; - log_out <= log_data; + dec1_log : process(clk) + begin + if rising_edge(clk) then + log_data <= std_ulogic_vector(to_unsigned(insn_type_t'pos(r.decode.insn_type), 6)) & + r.nia(5 downto 2) & + std_ulogic_vector(to_unsigned(unit_t'pos(r.decode.unit), 2)) & + r.valid; + end if; + end process; + log_out <= log_data; + end generate; end architecture behaviour; diff --git a/decode2.vhdl b/decode2.vhdl index d724874..62c574c 100644 --- a/decode2.vhdl +++ b/decode2.vhdl @@ -10,7 +10,9 @@ use work.insn_helpers.all; entity decode2 is generic ( - EX1_BYPASS : boolean := true + EX1_BYPASS : boolean := true; + -- Non-zero to enable log data collection + LOG_LENGTH : natural := 0 ); port ( clk : in std_ulogic; @@ -47,8 +49,6 @@ architecture behaviour of decode2 is signal deferred : std_ulogic; - signal log_data : std_ulogic_vector(9 downto 0); - type decode_input_reg_t is record reg_valid : std_ulogic; reg : gspr_index_t; @@ -415,18 +415,22 @@ begin e_out <= r.e; end process; - dec2_log : process(clk) + d2_log: if LOG_LENGTH > 0 generate + signal log_data : std_ulogic_vector(9 downto 0); begin - if rising_edge(clk) then - log_data <= r.e.nia(5 downto 2) & - r.e.valid & - stopped_out & - stall_out & - r.e.bypass_data3 & - r.e.bypass_data2 & - r.e.bypass_data1; - end if; - end process; - log_out <= log_data; + dec2_log : process(clk) + begin + if rising_edge(clk) then + log_data <= r.e.nia(5 downto 2) & + r.e.valid & + stopped_out & + stall_out & + r.e.bypass_data3 & + r.e.bypass_data2 & + r.e.bypass_data1; + end if; + end process; + log_out <= log_data; + end generate; end architecture behaviour; diff --git a/execute1.vhdl b/execute1.vhdl index fb760d1..2722570 100644 --- a/execute1.vhdl +++ b/execute1.vhdl @@ -12,7 +12,9 @@ use work.ppc_fx_insns.all; entity execute1 is generic ( - EX1_BYPASS : boolean := true + EX1_BYPASS : boolean := true; + -- Non-zero to enable log data collection + LOG_LENGTH : natural := 0 ); port ( clk : in std_ulogic; @@ -97,7 +99,6 @@ architecture behaviour of execute1 is -- signals for logging signal exception_log : std_ulogic; signal irq_valid_log : std_ulogic; - signal log_data : std_ulogic_vector(14 downto 0); type privilege_level is (USER, SUPER); type op_privilege_array is array(insn_type_t) of privilege_level; @@ -1083,21 +1084,25 @@ begin irq_valid_log <= irq_valid; end process; - ex1_log : process(clk) + e1_log: if LOG_LENGTH > 0 generate + signal log_data : std_ulogic_vector(14 downto 0); begin - if rising_edge(clk) then - log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) & - ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) & - exception_log & - irq_valid_log & - std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) & - "000" & - r.e.write_enable & - r.e.valid & - f_out.redirect & - r.busy & - flush_out; - end if; - end process; - log_out <= log_data; + ex1_log : process(clk) + begin + if rising_edge(clk) then + log_data <= ctrl.msr(MSR_EE) & ctrl.msr(MSR_PR) & + ctrl.msr(MSR_IR) & ctrl.msr(MSR_DR) & + exception_log & + irq_valid_log & + std_ulogic_vector(to_unsigned(irq_state_t'pos(ctrl.irq_state), 1)) & + "000" & + r.e.write_enable & + r.e.valid & + f_out.redirect & + r.busy & + flush_out; + end if; + end process; + log_out <= log_data; + end generate; end architecture behaviour; diff --git a/icache.vhdl b/icache.vhdl index 0aebbc2..3f1c15f 100644 --- a/icache.vhdl +++ b/icache.vhdl @@ -47,7 +47,9 @@ entity icache is -- L1 ITLB log_2(page_size) TLB_LG_PGSZ : positive := 12; -- Number of real address bits that we store - REAL_ADDR_BITS : positive := 56 + REAL_ADDR_BITS : positive := 56; + -- Non-zero to enable log data collection + LOG_LENGTH : natural := 0 ); port ( clk : in std_ulogic; @@ -207,9 +209,6 @@ architecture rtl of icache is signal access_ok : std_ulogic; signal use_previous : std_ulogic; - -- Output data to logger - signal log_data : std_ulogic_vector(53 downto 0); - -- Cache RAM interface type cache_ram_out_t is array(way_t) of cache_row_t; signal cache_out : cache_ram_out_t; @@ -729,31 +728,36 @@ begin end if; end process; - data_log: process(clk) - variable lway: way_t; - variable wstate: std_ulogic; + icache_log: if LOG_LENGTH > 0 generate + -- Output data to logger + signal log_data : std_ulogic_vector(53 downto 0); begin - if rising_edge(clk) then - lway := req_hit_way; - wstate := '0'; - if r.state /= IDLE then - wstate := '1'; + data_log: process(clk) + variable lway: way_t; + variable wstate: std_ulogic; + begin + if rising_edge(clk) then + lway := req_hit_way; + wstate := '0'; + if r.state /= IDLE then + wstate := '1'; + end if; + log_data <= i_out.valid & + i_out.insn & + wishbone_in.ack & + r.wb.adr(5 downto 3) & + r.wb.stb & r.wb.cyc & + wishbone_in.stall & + stall_out & + r.fetch_failed & + r.hit_nia(5 downto 2) & + wstate & + std_ulogic_vector(to_unsigned(lway, 3)) & + req_is_hit & req_is_miss & + access_ok & + ra_valid; end if; - log_data <= i_out.valid & - i_out.insn & - wishbone_in.ack & - r.wb.adr(5 downto 3) & - r.wb.stb & r.wb.cyc & - wishbone_in.stall & - stall_out & - r.fetch_failed & - r.hit_nia(5 downto 2) & - wstate & - std_ulogic_vector(to_unsigned(lway, 3)) & - req_is_hit & req_is_miss & - access_ok & - ra_valid; - end if; - end process; - log_out <= log_data; + end process; + log_out <= log_data; + end generate; end; diff --git a/loadstore1.vhdl b/loadstore1.vhdl index dd11221..0387e40 100644 --- a/loadstore1.vhdl +++ b/loadstore1.vhdl @@ -10,6 +10,10 @@ use work.common.all; -- We calculate the address in the first cycle entity loadstore1 is + generic ( + -- Non-zero to enable log data collection + LOG_LENGTH : natural := 0 + ); port ( clk : in std_ulogic; rst : in std_ulogic; @@ -85,8 +89,6 @@ architecture behave of loadstore1 is signal r, rin : reg_stage_t; signal lsu_sum : std_ulogic_vector(63 downto 0); - signal log_data : std_ulogic_vector(9 downto 0); - -- Generate byte enables from sizes function length_to_sel(length : in std_logic_vector(3 downto 0)) return std_ulogic_vector is begin @@ -515,18 +517,23 @@ begin end process; - ls1_log: process(clk) + l1_log: if LOG_LENGTH > 0 generate + signal log_data : std_ulogic_vector(9 downto 0); begin - if rising_edge(clk) then - log_data <= e_out.busy & - e_out.exception & - l_out.valid & - m_out.valid & - d_out.valid & - m_in.done & - r.dwords_done & - std_ulogic_vector(to_unsigned(state_t'pos(r.state), 3)); - end if; - end process; - log_out <= log_data; + ls1_log: process(clk) + begin + if rising_edge(clk) then + log_data <= e_out.busy & + e_out.exception & + l_out.valid & + m_out.valid & + d_out.valid & + m_in.done & + r.dwords_done & + std_ulogic_vector(to_unsigned(state_t'pos(r.state), 3)); + end if; + end process; + log_out <= log_data; + end generate; + end; diff --git a/register_file.vhdl b/register_file.vhdl index 260255e..10f28a4 100644 --- a/register_file.vhdl +++ b/register_file.vhdl @@ -7,7 +7,9 @@ use work.common.all; entity register_file is generic ( - SIM : boolean := false + SIM : boolean := false; + -- Non-zero to enable log data collection + LOG_LENGTH : natural := 0 ); port( clk : in std_logic; @@ -36,7 +38,6 @@ architecture behaviour of register_file is signal rd_port_b : std_ulogic_vector(63 downto 0); signal dbg_data : std_ulogic_vector(63 downto 0); signal dbg_ack : std_ulogic; - signal log_data : std_ulogic_vector(70 downto 0); begin -- synchronous writes register_write_0: process(clk) @@ -134,13 +135,18 @@ begin sim_dump_done <= '0'; end generate; - reg_log: process(clk) + rf_log: if LOG_LENGTH > 0 generate + signal log_data : std_ulogic_vector(70 downto 0); begin - if rising_edge(clk) then - log_data <= w_in.write_data & - w_in.write_enable & - w_in.write_reg; - end if; - end process; - log_out <= log_data; + reg_log: process(clk) + begin + if rising_edge(clk) then + log_data <= w_in.write_data & + w_in.write_enable & + w_in.write_reg; + end if; + end process; + log_out <= log_data; + end generate; + end architecture behaviour;