From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 18 Oct 2018 22:28:24 +0000 (+0100)
Subject: divuw
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=89505abcadae01ab60e08251690d5294f249cf26;p=riscv-isa-sim.git

divuw
---

diff --git a/riscv/insns/divuw.h b/riscv/insns/divuw.h
index 2fba815..34619f2 100644
--- a/riscv/insns/divuw.h
+++ b/riscv/insns/divuw.h
@@ -1,8 +1,8 @@
 require_extension('M');
 require_rv64;
-reg_t lhs = zext32(RS1);
-reg_t rhs = zext32(RS2);
-if(rhs == 0)
+sv_reg_t lhs = zext32(RS1);
+sv_reg_t rhs = zext32(RS2);
+if(rv_eq(rhs, sv_reg_t(0)))
   WRITE_RD(UINT64_MAX);
 else
   WRITE_RD(sext32(rv_div(lhs, rhs)));